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gupta409 / Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
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How to passed your testbench without any UVM_ERROR? #5

Open luantransnps opened 3 years ago

luantransnps commented 3 years ago

Hi gupta409,

I run your code with vcs simulator but get scoreboard issue about LOAD and MOVE command.

UVM_ERROR processor_scoreboard.sv(264) @ 11030000: uvm_test_top.env.sb [LOAD_FAIL] Actual Calculation=16384 Expected Calculation= 0 UVM_ERROR processor_scoreboard.sv(311) @ 46630000: uvm_test_top.env.sb [MOVE_FAIL] Actual Calculation= 154 Expected Calculation= 0 Please support me how to passed your testbench without any UVM_ERROR. Please refer to run log file attached.

Regards, Luan.

luantransnps commented 3 years ago

run.log

gupta409 commented 3 years ago

Looks like the code of the DUT has a missing file which is causing this issue. I do not have any backups for this project and we would need development of the Hazard Unit Controller again. If case you or someone else reading this on the internet looking for a small fun Verilog development project, is interested please consider forking this repo and developing the Hazard Unit referring to the documentation for the same. I can help with guidance on how this should be done.

genggf commented 2 years ago

Hi gupta409，

I found your paper on google, and I think your idea of using python script to help development is great, so I want to refer to your python script. I found that the python script is not included on github, Could you share it please!

Regards, gengfei

gupta409 commented 2 years ago

Hi,

Can you please point me to the paper you are talking about?

On Fri, Mar 4, 2022 at 12:40 PM genggf @.***> wrote:

Hi gupta409，

I found your paper on google, and I think your idea of using python script to help development is great, so I want to refer to your python script. I found that the python script is not included on github, Could you share it please!

Regards, gengfei

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genggf commented 2 years ago

Hi Gupta,

Thank you very much for your reply. The link to the paper is as follows: https://webthesis.biblio.polito.it/18053/1/tesi.pdf

I would like to refer to two places of your paper: ISA Database and RV Generator: If you want to refer to your ISA generation part, some ISAs are already included in your paper. If you need to extend the ISA, you can refer to the generated ISA part to quickly add your own extended ISA .Could you share the .py,.sv,*.csv files in the "ISA Database" and "RV Generator" chapters.

UVM Env Configurator:You use the interface to configure the simulation and present the simulation results, which is very cool, so I really want to refer to your GUI script.

In addition, some picture information of processor_scoreboard.sv is also given in your paper. By printing the information, it can be seen that the number of lines in the "processor_scoreboard.sv" file is very large, more than 1331 lines, which is much larger than the current "processor_scoreboard.scoreboard. sv", so if you have a backup, could you update this file as well, thank you very much!

Regards, gengfei

gupta409 commented 2 years ago

Hi gengfei,

The paper you mention only uses this repository as a reference. It is not associated with this particular repository. I would recommend you try to get in touch with the author of the paper you are looking at.

Thanks, Anish

genggf commented 2 years ago

Hi Anish, Thank you very much for your correction. I mistakenly thought that you are the author of this paper. I will continue to refer to your github project. If there are any questions, I will leave