"Missing symbol called" error with Yosys on Mac

[gussmith23]

(.venv) (.venv) fortyfort ➜  churchroad git:(ninehusky-even-more-operators) ✗ yosys -m yosys-plugin/churchroad.so -p 'read_verilog -sv tests/interpreter_tests/verilog/xilinx_ultrascale_plus/LUT6-modified.v; write_lakeroad'

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 |  yosys -- Yosys Open SYnthesis Suite                                       |
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 Yosys 0.36+42 (git sha1 70d35314d, clang 15.0.0 -fPIC -Os)

-- Running command `read_verilog -sv tests/interpreter_tests/verilog/xilinx_ultrascale_plus/LUT6-modified.v; write_lakeroad' --

1. Executing Verilog-2005 frontend: tests/interpreter_tests/verilog/xilinx_ultrascale_plus/LUT6-modified.v
Parsing SystemVerilog input from `tests/interpreter_tests/verilog/xilinx_ultrascale_plus/LUT6-modified.v' to AST representation.
Generating RTLIL representation for module `\LUT6'.
Successfully finished Verilog frontend.

2. Executing Lakeroad egglog backend.

3. Executing SPLICE pass (creating cells for signal splicing).
Splicing signals in module LUT6:
  Created spliced signal: { \I5 \I4 \I3 \I2 \I1 \I0 } -> $auto$splice.cc:140:get_spliced_signal$11

4. Executing SPLITNETS pass (splitting up multi-bit signals).
Removed 0 unused cells and 3 unused wires.
; wire declarations
dyld[83653]: missing symbol called
[1]    83653 abort      yosys -m yosys-plugin/churchroad.so -p 

[gussmith23]

Seems like recompiling the churchroad.so Yosys plugin might have fixed it.