Add Intel to evaluation

[gussmith23]

• [x] #107
  • [x] Figure out how to get Quartus to produce Verilog as output (why is not a default??) (answer: quartus_cdb mult_0_stage_signed_8_bit --vqm=tmp)
• [ ] #106
  • [ ] #105
• [x] #85
• [ ] #108
  • [x] https://github.com/uwsampl/lakeroad/issues/355
• [ ] #77

[gussmith23]

I'm trying to figure out what architecture to support. Given that we're using the free Quartus, it seems like these are the architectures I can find files for in Quartus's source:

• Arria II
• Cyclone IV, IVE, V, 10
• Max II, V However, some of these (maybe just Cyclone V?) are encrypted.