gussmith23
commented
2 years ago root@2d99cbf7d115:~# cat out/baseline/vivado/ugt32_2.log
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /root/out/baseline/vivado/ugt32_2.tcl
# set sv_source_file /root/instructions/src/ugt32_2.sv
# set modname ugt32_2
# set synth_opt_place_route_output_filepath /root/out/baseline/vivado/ugt32_2.sv
# set_part xczu3eg-sbva484-1-e
INFO: [Coretcl 2-1500] The part has been set to 'xczu3eg-sbva484-1-e' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
# read_verilog -sv ${sv_source_file}
# set_property top ${modname} [current_fileset]
# synth_design -mode out_of_context -directive default
Command: synth_design -mode out_of_context -directive default
Starting synth_design
Using part: xczu3eg-sbva484-1-e
Top: ugt32_2
Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 96
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Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4575.520 ; gain = 0.000 ; free physical = 41307 ; free virtual = 68160
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INFO: [Synth 8-6157] synthesizing module 'ugt32_2' [/root/instructions/src/ugt32_2.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'ugt32_2' (1#1) [/root/instructions/src/ugt32_2.sv:1]
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Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4575.520 ; gain = 0.000 ; free physical = 40919 ; free virtual = 67773
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Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4575.520 ; gain = 0.000 ; free physical = 40914 ; free virtual = 67768
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Start Loading Part and Timing Information
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Loading part: xczu3eg-sbva484-1-e
INFO: [Synth 8-6742] Reading net delay rules and data
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INFO: [Device 21-403] Loading part xczu3eg-sbva484-1-e
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4583.504 ; gain = 7.984 ; free physical = 40913 ; free virtual = 67767
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4583.504 ; gain = 7.984 ; free physical = 40905 ; free virtual = 67759
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No constraint files found.
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Start RTL Component Statistics
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Detailed RTL Component Info :
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Finished RTL Component Statistics
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Start Part Resource Summary
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Part Resources:
DSPs: 360 (col length:72)
BRAMs: 432 (col length: RAMB18 72 RAMB36 36)
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Finished Part Resource Summary
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No constraint files found.
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41171 ; free virtual = 68027
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No constraint files found.
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41170 ; free virtual = 68026
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41169 ; free virtual = 68026
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41174 ; free virtual = 68030
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41174 ; free virtual = 68030
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41174 ; free virtual = 68030
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41174 ; free virtual = 68030
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41174 ; free virtual = 68030
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41174 ; free virtual = 68030
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Start Writing Synthesis Report
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Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |CARRY8 | 2|
|2 |LUT4 | 32|
+------+-------+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 34|
+------+---------+-------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41174 ; free virtual = 68030
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Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.738 ; gain = 261.219 ; free physical = 41176 ; free virtual = 68032
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4836.746 ; gain = 261.219 ; free physical = 41176 ; free virtual = 68032
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4836.746 ; gain = 0.000 ; free physical = 41263 ; free virtual = 68119
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4836.746 ; gain = 0.000 ; free physical = 41190 ; free virtual = 68046
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: d4e828c5
INFO: [Common 17-83] Releasing license: Synthesis
15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 4836.746 ; gain = 261.246 ; free physical = 41391 ; free virtual = 68247
# read_xdc -mode out_of_context /root/out/baseline/vivado/ugt32_2.xdc
Parsing XDC File [/root/out/baseline/vivado/ugt32_2.xdc]
Finished Parsing XDC File [/root/out/baseline/vivado/ugt32_2.xdc]
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 4900.770 ; gain = 64.023 ; free physical = 41390 ; free virtual = 68247
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 12691c591
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4900.770 ; gain = 0.000 ; free physical = 41232 ; free virtual = 68089
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 12691c591
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 12691c591
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: a8e1df2e
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT.
Phase 4 BUFG optimization | Checksum: a8e1df2e
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: a8e1df2e
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: a8e1df2e
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
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Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
Ending Logic Optimization Task | Checksum: e2212e68
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41018 ; free virtual = 67875
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: e2212e68
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41215 ; free virtual = 68072
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: e2212e68
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41215 ; free virtual = 68072
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41215 ; free virtual = 68072
Ending Netlist Obfuscation Task | Checksum: e2212e68
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5049.770 ; gain = 0.000 ; free physical = 41215 ; free virtual = 68072
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg'
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6105.527 ; gain = 0.000 ; free physical = 40451 ; free virtual = 67308
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ca0cd0a3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6105.527 ; gain = 0.000 ; free physical = 40451 ; free virtual = 67308
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6105.527 ; gain = 0.000 ; free physical = 40451 ; free virtual = 67308
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ca0cd0a3
Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.08 . Memory (MB): peak = 6129.539 ; gain = 24.012 ; free physical = 40451 ; free virtual = 67308
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: d078a0b4
Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6161.555 ; gain = 56.027 ; free physical = 40427 ; free virtual = 67284
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: d078a0b4
Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6161.555 ; gain = 56.027 ; free physical = 40427 ; free virtual = 67284
Phase 1 Placer Initialization | Checksum: d078a0b4
Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6161.555 ; gain = 56.027 ; free physical = 40427 ; free virtual = 67284
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1.1 Partition Driven Placement
Phase 2.1.1.1 PBP: Partition Driven Placement
Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: d078a0b4
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6161.555 ; gain = 56.027 ; free physical = 40427 ; free virtual = 67283
Phase 2.1.1.2 PBP: Clock Region Placement
Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: d078a0b4
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.19 . Memory (MB): peak = 6161.555 ; gain = 56.027 ; free physical = 40427 ; free virtual = 67283
Phase 2.1.1.3 PBP: Compute Congestion
Phase 2.1.1.3 PBP: Compute Congestion | Checksum: d078a0b4
Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.54 . Memory (MB): peak = 6173.902 ; gain = 68.375 ; free physical = 40414 ; free virtual = 67271
Phase 2.1.1.4 PBP: Add part constraints
Phase 2.1.1.4 PBP: Add part constraints | Checksum: d078a0b4
Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.54 . Memory (MB): peak = 6173.902 ; gain = 68.375 ; free physical = 40414 ; free virtual = 67271
Phase 2.1.1 Partition Driven Placement | Checksum: d078a0b4
Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.55 . Memory (MB): peak = 6173.902 ; gain = 68.375 ; free physical = 40414 ; free virtual = 67271
Phase 2.1 Floorplanning | Checksum: d078a0b4
Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.55 . Memory (MB): peak = 6173.902 ; gain = 68.375 ; free physical = 40414 ; free virtual = 67271
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: d078a0b4
Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.55 . Memory (MB): peak = 6173.902 ; gain = 68.375 ; free physical = 40414 ; free virtual = 67271
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: d078a0b4
Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.55 . Memory (MB): peak = 6173.902 ; gain = 68.375 ; free physical = 40414 ; free virtual = 67271
Phase 2.4 Global Placement Core
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2.4 Global Placement Core | Checksum: 1a65edf9c
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40402 ; free virtual = 67258
Phase 2 Global Placement | Checksum: 1a65edf9c
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40402 ; free virtual = 67258
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1a65edf9c
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40399 ; free virtual = 67256
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67255
Phase 3.3 Small Shape DP
Phase 3.3.1 Small Shape Clustering
Phase 3.3.1 Small Shape Clustering | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40397 ; free virtual = 67253
Phase 3.3.2 Flow Legalize Slice Clusters
Phase 3.3.2 Flow Legalize Slice Clusters | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40397 ; free virtual = 67253
Phase 3.3.3 Slice Area Swap
Phase 3.3.3 Slice Area Swap | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40394 ; free virtual = 67250
Phase 3.3 Small Shape DP | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 3.4 Re-assign LUT pins
Phase 3.4 Re-assign LUT pins | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 3.5 Pipeline Register Optimization
Phase 3.5 Pipeline Register Optimization | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 3 Detail Placement | Checksum: 274c36ac7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 274c36ac7
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40393 ; free virtual = 67249
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 274c36ac7
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
________________________________________________________________________
| | Global Congestion | Long Congestion | Short Congestion |
| Direction | Region Size | Region Size | Region Size |
|___________|___________________|___________________|___________________|
| North| 1x1| 1x1| 1x1|
|___________|___________________|___________________|___________________|
| South| 1x1| 1x1| 1x1|
|___________|___________________|___________________|___________________|
| East| 1x1| 1x1| 1x1|
|___________|___________________|___________________|___________________|
| West| 1x1| 1x1| 1x1|
|___________|___________________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 274c36ac7
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 4.3 Placer Reporting | Checksum: 274c36ac7
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40398 ; free virtual = 67254
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 274c36ac7
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
Ending Placer Task | Checksum: 1ad9a5f06
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 6237.934 ; gain = 132.406 ; free physical = 40398 ; free virtual = 67254
INFO: [Common 17-83] Releasing license: Implementation
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 6237.934 ; gain = 1188.164 ; free physical = 40439 ; free virtual = 67296
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu3eg'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: e38d8e63 ConstDB: 0 ShapeSum: ca0cd0a3 RouteDB: 0
Nodegraph reading from file. Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.43 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40347 ; free virtual = 67204
WARNING: [Route 35-198] Port "a[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "a[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
WARNING: [Route 35-198] Port "b[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported.
Post Restoration Checksum: NetGraph: 3b1ad30f NumContArr: 4a7acd32 Constraints: 0 Timing: 0
Phase 1 Build RT Design | Checksum: 8595a041
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40343 ; free virtual = 67200
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 8595a041
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40303 ; free virtual = 67160
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 8595a041
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40303 ; free virtual = 67160
Phase 2.3 Global Clock Net Routing
Phase 2.3 Global Clock Net Routing | Checksum: 8595a041
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40304 ; free virtual = 67161
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 2
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 2
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 8595a041
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40305 ; free virtual = 67162
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 8595a041
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 6237.934 ; gain = 0.000 ; free physical = 40305 ; free virtual = 67162
Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40296 ; free virtual = 67153
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40296 ; free virtual = 67153
Phase 4 Rip-up And Reroute | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40296 ; free virtual = 67153
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40296 ; free virtual = 67153
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40296 ; free virtual = 67153
Phase 6 Post Hold Fix | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40296 ; free virtual = 67153
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40295 ; free virtual = 67152
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6245.965 ; gain = 8.031 ; free physical = 40293 ; free virtual = 67150
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6293.988 ; gain = 56.055 ; free physical = 40293 ; free virtual = 67150
Phase 10 Resolve XTalk
Phase 10 Resolve XTalk | Checksum: 11dd4f062
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6293.988 ; gain = 56.055 ; free physical = 40294 ; free virtual = 67151
Time taken to check if laguna hold fix is required (in secs): 0
Skip PhysOpt in Router because non-negative WNS value: 1e+30 .
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6293.988 ; gain = 56.055 ; free physical = 40344 ; free virtual = 67201
Routing Is Done.
realloc(): invalid pointer
Abnormal program termination (6)
Please check '/root/experiments/hs_err_pid89.log' for detailsroot@2d99cbf7d115:~# cat /root/experiments/hs_err_pid89.log
#
# An unexpected error has occurred (6)
#
Stack:
/lib/x86_64-linux-gnu/libc.so.6(+0x42520) [0x7f41a1c1a520]
/lib/x86_64-linux-gnu/libc.so.6(pthread_kill+0x12c) [0x7f41a1c6ea7c]
/lib/x86_64-linux-gnu/libc.so.6(raise+0x16) [0x7f41a1c1a476]
/lib/x86_64-linux-gnu/libc.so.6(abort+0xd3) [0x7f41a1c007f3]
/lib/x86_64-linux-gnu/libc.so.6(+0x896f6) [0x7f41a1c616f6]
/lib/x86_64-linux-gnu/libc.so.6(+0xa0d7c) [0x7f41a1c78d7c]
/lib/x86_64-linux-gnu/libc.so.6(realloc+0x36c) [0x7f41a1c7db2c]
/lib/x86_64-linux-gnu/libudev.so.1(+0x156d7) [0x7f41a28776d7]
/lib/x86_64-linux-gnu/libudev.so.1(+0x1baeb) [0x7f41a287daeb]
/lib/x86_64-linux-gnu/libudev.so.1(+0x75cf) [0x7f41a28695cf]
/lib/x86_64-linux-gnu/libudev.so.1(+0x7b3b) [0x7f41a2869b3b]
/lib/x86_64-linux-gnu/libudev.so.1(+0x10162) [0x7f41a2872162]
/lib/x86_64-linux-gnu/libudev.so.1(+0x105a3) [0x7f41a28725a3]
/lib/x86_64-linux-gnu/libudev.so.1(udev_enumerate_scan_devices+0x2a1) [0x7f41a2873311]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libXil_lmgr11.so(+0x129015) [0x7f4197529015]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libXil_lmgr11.so(xilinxd_52bd866351b78202+0x9) [0x7f4197529499]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libXil_lmgr11.so(+0xd6317) [0x7f41974d6317]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libXil_lmgr11.so(xilinxd_52bd862318b59a70+0x86) [0x7f41974d60d6]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libXil_lmgr11.so(+0xc364f) [0x7f41974c364f]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libXil_lmgr11.so(xilinxd_52bd9e9e1c8e52fb+0x1b) [0x7f41974cd3eb]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libXil_lmgr11.so(xilinxd_52bd700d1bd3c616+0x30) [0x7f41974cd480]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commonxillic.so(XilReg::Utils::GetHostInfo[abi:cxx11](XilReg::Utils::HostInfoType, bool) const+0x1c8) [0x7f419c6776d8]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commonxillic.so(XilReg::Utils::GetHostInfoFormatted[abi:cxx11](XilReg::Utils::HostInfoType, bool) const+0x52) [0x7f419c67b2e2]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commonxillic.so(XilReg::Utils::GetHostInfo[abi:cxx11]() const+0x183) [0x7f419c67b5a3]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commonxillic.so(XilReg::Utils::GetRegInfo(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, bool, bool)+0xc6) [0x7f419c688856]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commonxillic.so(XilReg::Utils::GetRegInfoWebTalk(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)+0x60) [0x7f419c688ae0]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_project.so(HAPRWebtalkHelper::getRegistrationId[abi:cxx11]() const+0x3a) [0x7f40df0d63da]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_project.so(HAPRWebtalkHelper::HAPRWebtalkHelper(HAPRProject*, HAPRDesign*, HWEWebtalkMgr*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)+0x158) [0x7f40df0d6cd8]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_project.so(HAPRDesign::prepAndTransmitWebtalkData(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, bool)+0x69) [0x7f40def6d299]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_vivadotasks.so(+0x5df30f) [0x7f40c41df30f]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_vivadotasks.so(+0x5e21d9) [0x7f40c41e21d9]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_common.so(+0xa80712) [0x7f41a3480712]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(+0x3356f) [0x7f419ba3356f]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(+0x34bf8) [0x7f419ba34bf8]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalEx+0x13) [0x7f419ba35163]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(Tcl_FSEvalFileEx+0x1da) [0x7f419ba99d2a]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commontasks.so(+0x2082ed) [0x7f4118a082ed]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_common.so(+0xa80712) [0x7f41a3480712]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(+0x3356f) [0x7f419ba3356f]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7f419ba336a2]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7f419ba354c2]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commontasks.so(+0x24d299) [0x7f4118a4d299]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commontasks.so(+0x24ed0e) [0x7f4118a4ed0e]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_common.so(+0xa80712) [0x7f41a3480712]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(+0x3356f) [0x7f419ba3356f]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(Tcl_EvalObjv+0x32) [0x7f419ba336a2]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(TclEvalObjEx+0x322) [0x7f419ba354c2]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_commonmain.so(+0xce23) [0x7f41a260ce23]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/libtcl8.5.so(Tcl_Main+0x1d0) [0x7f419baa02f0]
/tools/Xilinx/Vivado/2021.2/lib/lnx64.o/librdi_common.so(+0xac239b) [0x7f41a34c239b]
/lib/x86_64-linux-gnu/libc.so.6(+0x94b43) [0x7f41a1c6cb43]
/lib/x86_64-linux-gnu/libc.so.6(clone+0x44) [0x7f41a1cfdbb4]
I ran into this problem a while ago. I started using
route_design -release_memorybecause the flag prevented a crash in the Docker container. Turns out it prevents a crash because it doesn't run routing at all. Whoops.Without the flag, we get the crash. So have to investigate this.