Investigate bug Vishal is getting from Lakeroad Xilinx compilation

[vcanumalla]

robustness_experiments:submulxor_3_stage_unsigned_9_bit:lakeroad-xilinx
Warning: No driver for signal \stage1 [17:9].
Warning: No driver for signal \stage2 [17:9].
match: no matching clause for (list (cons (var "a" 9) 9) (cons (var "b" 9) 9) (cons (var "c" 9) 9) (cons (var "d" 9) 9))
  location...:
   lakeroad/racket/sketches.rkt:243:8
  context...:
   /home/vishalc/lakeroad-evaluation/lakeroad/racket/sketches.rkt:202:0: single-dsp-sketch-generator
   body of "/home/vishalc/lakeroad-evaluation/lakeroad/bin/main.rkt"
ERROR:root: racket /home/vishalc/lakeroad-evaluation/lakeroad/bin/main.rkt --out-format verilog --template dsp --module-name output --out-filepath /home/vishalc/lakeroad-evaluation/out/robustness_experiments/submulxor_3_stage_unsigned_9_bit/lakeroad-xilinx/output.v --architecture xilinx-ultrascale-plus --verilog-module-filepath /home/vishalc/lakeroad-evaluation/robustness-testing-verilog-files/generated/submulxor_3_stage_unsigned_9_bit.sv --verilog-module-out-signal out:9 --top-module-name submulxor_3_stage_unsigned_9_bit --initiation-interval 3 --input-signal a:9 --input-signal b:9 --input-signal c:9 --input-signal d:9 --clock-name clk
TaskError - taskid:robustness_experiments:submulxor_3_stage_unsigned_9_bit:lakeroad-xilinx
PythonAction Error
Traceback (most recent call last):
  File "/home/vishalc/lakeroad-evaluation/venv/lib/python3.10/site-packages/doit/action.py", line 461, in execute
    returned_value = self.py_callable(*self.args, **kwargs)
  File "/home/vishalc/lakeroad-evaluation/python/lakeroad.py", line 291, in invoke_lakeroad
    proc.check_returncode()
  File "/home/vishalc/.pyenv/versions/3.10.6/lib/python3.10/subprocess.py", line 456, in check_returncode
    raise CalledProcessError(self.returncode, self.args, self.stdout,
subprocess.CalledProcessError: Command '['racket', '/home/vishalc/lakeroad-evaluation/lakeroad/bin/main.rkt', '--out-format', 'verilog', '--template', 'dsp', '--module-name', 'output', '--out-filepath', PosixPath('/home/vishalc/lakeroad-evaluation/out/robustness_experiments/submulxor_3_stage_unsigned_9_bit/lakeroad-xilinx/output.v'), '--architecture', 'xilinx-ultrascale-plus', '--verilog-module-filepath', '/home/vishalc/lakeroad-evaluation/robustness-testing-verilog-files/generated/submulxor_3_stage_unsigned_9_bit.sv', '--verilog-module-out-signal', 'out:9', '--top-module-name', 'submulxor_3_stage_unsigned_9_bit', '--initiation-interval', '3', '--input-signal', 'a:9', '--input-signal', 'b:9', '--input-signal', 'c:9', '--input-signal', 'd:9', '--clock-name', 'clk']' returned non-zero exit status 1.```

[gussmith23]

Updating Lakeroad fixed this