Build fails with an error:

[lesley-byte]

`Starting FPGA Toolchain Starting Yosys CST Checking /----------------------------------------------------------------------------\			yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2020 Claire Xenia Wolf claire@yosyshq.com
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 \----------------------------------------------------------------------------/
Parsing FPGA.v
    - Module top parsed
Checking if all ports are defined in constraints file
All Ports are defined

Finished CST Checking Starting Synthesys with Yosys (Gowin) Step 1: Executing Verilog-2005 frontend: c:\Users\phosp\FPGA\FPGA.v Step 2: Executing SYNTH_GOWIN pass. Step 2.1: Executing Verilog-2005 frontend: c:\PROGRA~1\OSS-CA~1\bin../share/yosys/gowin/cells_sim.v Step 2.2: Executing HIERARCHY pass (managing design hierarchy). Step 2.3: Executing PROC pass (convert processes to netlists). Step 2.4: Executing FLATTEN pass (flatten design). Step 2.5: Executing TRIBUF pass. Step 2.6: Executing DEMINOUT pass (demote inout ports to input or output). Step 2.7: Executing SYNTH pass. Step 2.8: Executing MEMORY_LIBMAP pass (mapping memories to cells). Step 2.9: Executing TECHMAP pass (map to technology primitives). Step 2.10: Executing OPT pass (performing simple optimizations). Step 2.11: Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Step 2.12: Executing OPT pass (performing simple optimizations). Step 2.13: Executing TECHMAP pass (map to technology primitives). Step 2.14: Executing OPT pass (performing simple optimizations). Step 2.15: Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). Step 2.16: Executing OPT_CLEAN pass (remove unused cells and wires). Step 2.17: Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Step 2.18: Executing TECHMAP pass (map to technology primitives). Step 2.19: Executing OPT_EXPR pass (perform const folding). Step 2.20: Executing SIMPLEMAP pass (map simple cells to gate primitives). Step 2.21: Executing ABC pass (technology mapping using ABC). Step 2.22: Executing TECHMAP pass (map to technology primitives). Step 2.23: Executing OPT_LUT_INS pass (discard unused LUT inputs). Step 2.24: Executing SETUNDEF pass (replace undef values with defined constants). Step 2.25: Executing HILOMAP pass (mapping to constant drivers). Step 2.26: Executing AUTONAME pass. Step 2.27: Executing HIERARCHY pass (managing design hierarchy). Step 2.28: Printing statistics. Step 2.29: Executing CHECK pass (checking for obvious problems). Step 2.30: Executing JSON backend.

Summary
    Number of wires:                 643
    Number of wire bits:             781
    Number of public wires:          643
    Number of public wire bits:      781
    Number of memories:                0
    Number of memory bits:             0
    Number of processes:               0
    Number of cells:                 720
        ALU                           24
        DFFR                          24
        DFFRE                         14
        DFFSE                          2
        GND                            1
        IBUF                           1
        LUT1                         295
        LUT4                          55
        MUX2_LUT5                    168
        MUX2_LUT6                     84
        MUX2_LUT7                     26
        MUX2_LUT8                      9
        OBUF                          16
        VCC                            1

Finished Synthesys Starting PnR with NextPnR Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5 Packing constants.. Packing Shadow RAM.. Packing GSR.. Packing IOs.. Packing diff IOs.. Packing IO logic.. Packing wide LUTs.. Packing LUT5s.. Packing LUT6s.. Packing LUT7s.. Packing LUT8s.. Packing ALUs.. Packing LUT-FFs.. Packing non-LUT FFs.. Packing PLLs.. Checksum: 0x665afea9 Annotating ports with timing budgets for target frequency 27.00 MHz Checksum: 0x665afea9 Placed 17 cells based on constraints. Creating initial analytic placement for 107 cells, random placement wirelen = 3894. Running main analytical placer, max placement attempts per cell = 65341. HeAP Placer Time: 0.18s Running simulated annealing placer for refinement. SA placement time 0.50s Max frequency for clock 'clk_IBUF_I_O': 137.76 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 18.69 ns Checksum: 0x9191bee8 Find global nets... Routing globals... Routing.. Setting up routing queue. Routing 1299 arcs. Routing complete. Router1 time 1.41s Checksum: 0x5a57288d Max frequency for clock 'clk_IBUF_I_O': 166.14 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 11.97 ns Program finished normally.

Device Utilisation:
    VCC:               1/    1   100%
    SLICE:           416/ 8640     4%
    IOB:              17/  274     6%
    ODDR:              0/  274     0%
    MUX2_LUT5:       168/ 4320     3%
    MUX2_LUT6:        84/ 2160     3%
    MUX2_LUT7:        26/ 1080     2%
    MUX2_LUT8:         9/ 1056     0%
    GND:               1/    1   100%
    RAMW:              0/  270     0%
    GSR:               1/    1   100%
    OSC:               0/    1     0%
    rPLL:              0/    2     0%

Finished PnR Starting Bitstream Generation with Apicula failed to create process. Finished Bitstream Generation Starting FPGA Programming with OpenFPGALoader write to flash Jtag frequency : requested 6.00MHz found 1 devices index 0: idcode 0x100481b manufacturer Gowin family GW1N model GW1N(R)-9C irlength 8 File type : fs Error: Error: Failed to claim FPGA device: Error: fail to open c:\Users\phosp\FPGA\FPGA.fs Finished FPGA Programming Task finished with errors exiting Toolchain Completed `

[lesley-byte]

When I create a file named FPGA.fs it fails with a different error:

`Starting FPGA Toolchain Starting Yosys CST Checking /----------------------------------------------------------------------------\			yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2020 Claire Xenia Wolf claire@yosyshq.com
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 \----------------------------------------------------------------------------/
Parsing FPGA.v
    - Module top parsed
Checking if all ports are defined in constraints file
All Ports are defined

Finished CST Checking Starting Synthesys with Yosys (Gowin) Step 1: Executing Verilog-2005 frontend: c:\Users\phosp\FPGA\FPGA.v Step 2: Executing SYNTH_GOWIN pass. Step 2.1: Executing Verilog-2005 frontend: c:\PROGRA~1\OSS-CA~1\bin../share/yosys/gowin/cells_sim.v Step 2.2: Executing HIERARCHY pass (managing design hierarchy). Step 2.3: Executing PROC pass (convert processes to netlists). Step 2.4: Executing FLATTEN pass (flatten design). Step 2.5: Executing TRIBUF pass. Step 2.6: Executing DEMINOUT pass (demote inout ports to input or output). Step 2.7: Executing SYNTH pass. Step 2.8: Executing MEMORY_LIBMAP pass (mapping memories to cells). Step 2.9: Executing TECHMAP pass (map to technology primitives). Step 2.10: Executing OPT pass (performing simple optimizations). Step 2.11: Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Step 2.12: Executing OPT pass (performing simple optimizations). Step 2.13: Executing TECHMAP pass (map to technology primitives). Step 2.14: Executing OPT pass (performing simple optimizations). Step 2.15: Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). Step 2.16: Executing OPT_CLEAN pass (remove unused cells and wires). Step 2.17: Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Step 2.18: Executing TECHMAP pass (map to technology primitives). Step 2.19: Executing OPT_EXPR pass (perform const folding). Step 2.20: Executing SIMPLEMAP pass (map simple cells to gate primitives). Step 2.21: Executing ABC pass (technology mapping using ABC). Step 2.22: Executing TECHMAP pass (map to technology primitives). Step 2.23: Executing OPT_LUT_INS pass (discard unused LUT inputs). Step 2.24: Executing SETUNDEF pass (replace undef values with defined constants). Step 2.25: Executing HILOMAP pass (mapping to constant drivers). Step 2.26: Executing AUTONAME pass. Step 2.27: Executing HIERARCHY pass (managing design hierarchy). Step 2.28: Printing statistics. Step 2.29: Executing CHECK pass (checking for obvious problems). Step 2.30: Executing JSON backend.

Summary
    Number of wires:                 643
    Number of wire bits:             781
    Number of public wires:          643
    Number of public wire bits:      781
    Number of memories:                0
    Number of memory bits:             0
    Number of processes:               0
    Number of cells:                 720
        ALU                           24
        DFFR                          24
        DFFRE                         14
        DFFSE                          2
        GND                            1
        IBUF                           1
        LUT1                         295
        LUT4                          55
        MUX2_LUT5                    168
        MUX2_LUT6                     84
        MUX2_LUT7                     26
        MUX2_LUT8                      9
        OBUF                          16
        VCC                            1

Finished Synthesys Starting PnR with NextPnR Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5 Packing constants.. Packing Shadow RAM.. Packing GSR.. Packing IOs.. Packing diff IOs.. Packing IO logic.. Packing wide LUTs.. Packing LUT5s.. Packing LUT6s.. Packing LUT7s.. Packing LUT8s.. Packing ALUs.. Packing LUT-FFs.. Packing non-LUT FFs.. Packing PLLs.. Checksum: 0x665afea9 Annotating ports with timing budgets for target frequency 27.00 MHz Checksum: 0x665afea9 Placed 17 cells based on constraints. Creating initial analytic placement for 107 cells, random placement wirelen = 3894. Running main analytical placer, max placement attempts per cell = 65341. HeAP Placer Time: 0.19s Running simulated annealing placer for refinement. SA placement time 0.49s Max frequency for clock 'clk_IBUF_I_O': 137.76 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 18.69 ns Checksum: 0x9191bee8 Find global nets... Routing globals... Routing.. Setting up routing queue. Routing 1299 arcs. Routing complete. Router1 time 1.44s Checksum: 0x5a57288d Max frequency for clock 'clk_IBUF_I_O': 166.14 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 11.97 ns Program finished normally.

Device Utilisation:
    VCC:               1/    1   100%
    SLICE:           416/ 8640     4%
    IOB:              17/  274     6%
    ODDR:              0/  274     0%
    MUX2_LUT5:       168/ 4320     3%
    MUX2_LUT6:        84/ 2160     3%
    MUX2_LUT7:        26/ 1080     2%
    MUX2_LUT8:         9/ 1056     0%
    GND:               1/    1   100%
    RAMW:              0/  270     0%
    GSR:               1/    1   100%
    OSC:               0/    1     0%
    rPLL:              0/    2     0%

Finished PnR Starting Bitstream Generation with Apicula failed to create process. Finished Bitstream Generation Starting FPGA Programming with OpenFPGALoader write to flash Jtag frequency : requested 6.00MHz found 1 devices index 0: idcode 0x100481b manufacturer Gowin family GW1N model GW1N(R)-9C irlength 8 File type : fs Parse file Parse c:\Users\phosp\FPGA\FPGA.fs: Warning: IDCODE not found

Warning: Unknown IDCODE
_**Error: Error: Failed to claim FPGA device: stoul**_

Finished FPGA Programming Task finished with errors exiting Toolchain Completed`

[h4ck3rb0x]

Going down the output, it looks like this is where it (first) breaks...

Starting Bitstream Generation with Apicula failed to create process. Finished Bitstream Generation

So I would check your Apicula setup (files, environment variables, etc)

Since bitstream generation failed, there is no bitstream output file and the program step fails because it doesn't have a bitstream to program.

Hopefully that will break you through.

Best regards, Team HackerBoxes @.*** www.HackerBoxes.com

On Fri, Feb 24, 2023 at 12:13 PM Lesley-Byte @.***> wrote:

`Starting FPGA Toolchain Starting Yosys CST Checking

/----------------------------------------------------------------------------			yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2020 Claire Xenia Wolf @.***
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

----------------------------------------------------------------------------/ Parsing FPGA.v

• Module top parsed Checking if all ports are defined in constraints file All Ports are defined Finished CST Checking Starting Synthesys with Yosys (Gowin) Step 1: Executing Verilog-2005 frontend: c:\Users\phosp\FPGA\FPGA.v Step 2: Executing SYNTH_GOWIN pass. Step 2.1: Executing Verilog-2005 frontend: c:\PROGRA1\OSS-CA 1\bin../share/yosys/gowin/cells_sim.v Step 2.2: Executing HIERARCHY pass (managing design hierarchy). Step 2.3: Executing PROC pass (convert processes to netlists). Step 2.4: Executing FLATTEN pass (flatten design). Step 2.5: Executing TRIBUF pass. Step 2.6: Executing DEMINOUT pass (demote inout ports to input or output). Step 2.7: Executing SYNTH pass. Step 2.8: Executing MEMORY_LIBMAP pass (mapping memories to cells). Step 2.9: Executing TECHMAP pass (map to technology primitives). Step 2.10: Executing OPT pass (performing simple optimizations). Step 2.11: Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Step 2.12: Executing OPT pass (performing simple optimizations). Step 2.13: Executing TECHMAP pass (map to technology primitives). Step 2.14: Executing OPT pass (performing simple optimizations). Step 2.15: Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). Step 2.16: Executing OPT_CLEAN pass (remove unused cells and wires). Step 2.17: Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Step 2.18: Executing TECHMAP pass (map to technology primitives). Step 2.19: Executing OPT_EXPR pass (perform const folding). Step 2.20: Executing SIMPLEMAP pass (map simple cells to gate primitives). Step 2.21: Executing ABC pass (technology mapping using ABC). Step 2.22: Executing TECHMAP pass (map to technology primitives). Step 2.23: Executing OPT_LUT_INS pass (discard unused LUT inputs). Step 2.24: Executing SETUNDEF pass (replace undef values with defined constants). Step 2.25: Executing HILOMAP pass (mapping to constant drivers). Step 2.26: Executing AUTONAME pass. Step 2.27: Executing HIERARCHY pass (managing design hierarchy). Step 2.28: Printing statistics. Step 2.29: Executing CHECK pass (checking for obvious problems). Step 2.30: Executing JSON backend.

Summary Number of wires: 643 Number of wire bits: 781 Number of public wires: 643 Number of public wire bits: 781 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 720 ALU 24 DFFR 24 DFFRE 14 DFFSE 2 GND 1 IBUF 1 LUT1 295 LUT4 55 MUX2_LUT5 168 MUX2_LUT6 84 MUX2_LUT7 26 MUX2_LUT8 9 OBUF 16 VCC 1

Finished Synthesys Starting PnR with NextPnR Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5 Packing constants.. Packing Shadow RAM.. Packing GSR.. Packing IOs.. Packing diff IOs.. Packing IO logic.. Packing wide LUTs.. Packing LUT5s.. Packing LUT6s.. Packing LUT7s.. Packing LUT8s.. Packing ALUs.. Packing LUT-FFs.. Packing non-LUT FFs.. Packing PLLs.. Checksum: 0x665afea9 Annotating ports with timing budgets for target frequency 27.00 MHz Checksum: 0x665afea9 Placed 17 cells based on constraints. Creating initial analytic placement for 107 cells, random placement wirelen = 3894. Running main analytical placer, max placement attempts per cell = 65341. HeAP Placer Time: 0.18s Running simulated annealing placer for refinement. SA placement time 0.50s Max frequency for clock 'clk_IBUF_I_O': 137.76 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 18.69 ns Checksum: 0x9191bee8 Find global nets... Routing globals... Routing.. Setting up routing queue. Routing 1299 arcs. Routing complete. Router1 time 1.41s Checksum: 0x5a57288d Max frequency for clock 'clk_IBUF_I_O': 166.14 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 11.97 ns Program finished normally.

Device Utilisation: VCC: 1/ 1 100% SLICE: 416/ 8640 4% IOB: 17/ 274 6% ODDR: 0/ 274 0% MUX2_LUT5: 168/ 4320 3% MUX2_LUT6: 84/ 2160 3% MUX2_LUT7: 26/ 1080 2% MUX2_LUT8: 9/ 1056 0% GND: 1/ 1 100% RAMW: 0/ 270 0% GSR: 1/ 1 100% OSC: 0/ 1 0% rPLL: 0/ 2 0%

Finished PnR Starting Bitstream Generation with Apicula failed to create process. Finished Bitstream Generation Starting FPGA Programming with OpenFPGALoader write to flash Jtag frequency : requested 6.00MHz found 1 devices index 0: idcode 0x100481b manufacturer Gowin family GW1N model GW1N(R)-9C irlength 8 File type : fs Error: Error: Failed to claim FPGA device: Error: fail to open c:\Users\phosp\FPGA\FPGA.fs Finished FPGA Programming Task finished with errors exiting Toolchain Completed `

— Reply to this email directly, view it on GitHub https://github.com/h4ck3rb0x/HackerBox0088/issues/1, or unsubscribe https://github.com/notifications/unsubscribe-auth/A522X7OQIDPGGS4XWNXV6O3WZDT2RANCNFSM6AAAAAAVHEKR74 . You are receiving this because you are subscribed to this thread.Message ID: @.***>

[lesley-byte]

apicula is a python package. It doesn't have a setup file. I'm going to try this on a mac and see if it works better that way.

If that doesn't work then will try on a linux machine. I can also create a virtual machine so something will hopefully have apicula with the right setup. I can even create a virtual machine.

[lesley-byte]

I installed apicula with pip install apycula...still broken.

I tried this on a mac and my mac deleted oss-cad-suite because it thinks its malicious. I might take a break and see if anyone else is having the same issue. maybe it only works on windowsv10... and not 11 I will try that too

[lesley-byte]

ok I tried it on my older windows 10 computer and the error changed to:

`Starting FPGA Toolchain Starting Yosys CST Checking /----------------------------------------------------------------------------\			yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2020 Claire Xenia Wolf claire@yosyshq.com
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 \----------------------------------------------------------------------------/
Parsing counter.v
    - Module top parsed
Checking if all ports are defined in constraints file
All Ports are defined

Finished CST Checking Starting Synthesys with Yosys (Gowin) Step 1: Executing Verilog-2005 frontend: c:\Users\phosp\FPGA\FPGA\counter.v Step 2: Executing SYNTH_GOWIN pass. Step 2.1: Executing Verilog-2005 frontend: c:\Users\phosp\FPGA\OSS-CA~1\bin../share/yosys/gowin/cells_sim.v Step 2.2: Executing HIERARCHY pass (managing design hierarchy). Step 2.3: Executing PROC pass (convert processes to netlists). Step 2.4: Executing FLATTEN pass (flatten design). Step 2.5: Executing TRIBUF pass. Step 2.6: Executing DEMINOUT pass (demote inout ports to input or output). Step 2.7: Executing SYNTH pass. Step 2.8: Executing MEMORY_LIBMAP pass (mapping memories to cells). Step 2.9: Executing TECHMAP pass (map to technology primitives). Step 2.10: Executing OPT pass (performing simple optimizations). Step 2.11: Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Step 2.12: Executing OPT pass (performing simple optimizations). Step 2.13: Executing TECHMAP pass (map to technology primitives). Step 2.14: Executing OPT pass (performing simple optimizations). Step 2.15: Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). Step 2.16: Executing OPT_CLEAN pass (remove unused cells and wires). Step 2.17: Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Step 2.18: Executing TECHMAP pass (map to technology primitives). Step 2.19: Executing OPT_EXPR pass (perform const folding). Step 2.20: Executing SIMPLEMAP pass (map simple cells to gate primitives). Step 2.21: Executing ABC pass (technology mapping using ABC). Step 2.22: Executing TECHMAP pass (map to technology primitives). Step 2.23: Executing OPT_LUT_INS pass (discard unused LUT inputs). Step 2.24: Executing SETUNDEF pass (replace undef values with defined constants). Step 2.25: Executing HILOMAP pass (mapping to constant drivers). Step 2.26: Executing AUTONAME pass. Step 2.27: Executing HIERARCHY pass (managing design hierarchy). Step 2.28: Printing statistics. Step 2.29: Executing CHECK pass (checking for obvious problems). Step 2.30: Executing JSON backend.

Summary
    Number of wires:                 223
    Number of wire bits:             345
    Number of public wires:          223
    Number of public wire bits:      345
    Number of memories:                0
    Number of memory bits:             0
    Number of processes:               0
    Number of cells:                 285
        ALU                           30
        DFFE                           6
        DFFR                          24
        GND                            1
        IBUF                           1
        LUT1                          90
        LUT4                          36
        MUX2_LUT5                     60
        MUX2_LUT6                     30
        OBUF                           6
        VCC                            1

Finished Synthesys Starting PnR with NextPnR Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5 Packing constants.. Packing Shadow RAM.. Packing GSR.. Packing IOs.. Packing diff IOs.. Packing IO logic.. Packing wide LUTs.. Packing LUT5s.. Packing LUT6s.. Packing LUT7s.. Packing LUT8s.. Packing ALUs.. Packing LUT-FFs.. Packing non-LUT FFs.. Packing PLLs.. Checksum: 0x77743ab0 Annotating ports with timing budgets for target frequency 27.00 MHz Checksum: 0x77743ab0 Placed 7 cells based on constraints. Creating initial analytic placement for 71 cells, random placement wirelen = 2954. Running main analytical placer, max placement attempts per cell = 10512. HeAP Placer Time: 0.19s Running simulated annealing placer for refinement. SA placement time 0.14s Max frequency for clock 'clk_IBUF_I_O': 179.99 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 7.56 ns Checksum: 0xdbf4f580 Find global nets... Routing globals... Routing.. Setting up routing queue. Routing 603 arcs. Routing complete. Router1 time 2.46s Checksum: 0x29a9a997 Max frequency for clock 'clk_IBUF_I_O': 213.27 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 5.65 ns Program finished normally.

Device Utilisation:
    VCC:               1/    1   100%
    SLICE:           190/ 8640     2%
    IOB:               7/  274     2%
    ODDR:              0/  274     0%
    MUX2_LUT5:        60/ 4320     1%
    MUX2_LUT6:        30/ 2160     1%
    MUX2_LUT7:         0/ 1080     0%
    MUX2_LUT8:         0/ 1056     0%
    GND:               1/    1   100%
    RAMW:              0/  270     0%
    GSR:               1/    1   100%
    OSC:               0/    1     0%
    rPLL:              0/    2     0%

Finished PnR Starting Bitstream Generation with Apicula testing. You are advised not to use it for production.

Finished Bitstream Generation Starting FPGA Programming with OpenFPGALoader write to flash _Error: unable to open ftdi device: -4 (usb_open() failed) Error: JTAG init failed with: unable to open ftdi device_ Finished FPGA Programming Task finished with errors exiting Toolchain Completed`

[lesley-byte]

so I tried to re-install the driver again and that didn't work. I'm going to keep trying. I guess my windows 11 machine wasn't ready for apicula stuff or maybe I've installed it before without realizing it on my older machine. or who knows.

[lesley-byte]

ok after that I installed the windows driver one more time and suddenly it works but with a checksum error:

Starting FPGA Toolchain Starting Yosys CST Checking /----------------------------------------------------------------------------\			yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2020 Claire Xenia Wolf claire@yosyshq.com
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 \----------------------------------------------------------------------------/
Parsing counter.v
    - Module top parsed
Checking if all ports are defined in constraints file
All Ports are defined

Finished CST Checking Starting Synthesys with Yosys (Gowin) Step 1: Executing Verilog-2005 frontend: c:\Users\phosp\FPGA\FPGA\counter.v Step 2: Executing SYNTH_GOWIN pass. Step 2.1: Executing Verilog-2005 frontend: c:\Users\phosp\FPGA\OSS-CA~1\bin../share/yosys/gowin/cells_sim.v Step 2.2: Executing HIERARCHY pass (managing design hierarchy). Step 2.3: Executing PROC pass (convert processes to netlists). Step 2.4: Executing FLATTEN pass (flatten design). Step 2.5: Executing TRIBUF pass. Step 2.6: Executing DEMINOUT pass (demote inout ports to input or output). Step 2.7: Executing SYNTH pass. Step 2.8: Executing MEMORY_LIBMAP pass (mapping memories to cells). Step 2.9: Executing TECHMAP pass (map to technology primitives). Step 2.10: Executing OPT pass (performing simple optimizations). Step 2.11: Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Step 2.12: Executing OPT pass (performing simple optimizations). Step 2.13: Executing TECHMAP pass (map to technology primitives). Step 2.14: Executing OPT pass (performing simple optimizations). Step 2.15: Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). Step 2.16: Executing OPT_CLEAN pass (remove unused cells and wires). Step 2.17: Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Step 2.18: Executing TECHMAP pass (map to technology primitives). Step 2.19: Executing OPT_EXPR pass (perform const folding). Step 2.20: Executing SIMPLEMAP pass (map simple cells to gate primitives). Step 2.21: Executing ABC pass (technology mapping using ABC). Step 2.22: Executing TECHMAP pass (map to technology primitives). Step 2.23: Executing OPT_LUT_INS pass (discard unused LUT inputs). Step 2.24: Executing SETUNDEF pass (replace undef values with defined constants). Step 2.25: Executing HILOMAP pass (mapping to constant drivers). Step 2.26: Executing AUTONAME pass. Step 2.27: Executing HIERARCHY pass (managing design hierarchy). Step 2.28: Printing statistics. Step 2.29: Executing CHECK pass (checking for obvious problems). Step 2.30: Executing JSON backend.

Summary
    Number of wires:                 223
    Number of wire bits:             345
    Number of public wires:          223
    Number of public wire bits:      345
    Number of memories:                0
    Number of memory bits:             0
    Number of processes:               0
    Number of cells:                 285
        ALU                           30
        DFFE                           6
        DFFR                          24
        GND                            1
        IBUF                           1
        LUT1                          90
        LUT4                          36
        MUX2_LUT5                     60
        MUX2_LUT6                     30
        OBUF                           6
        VCC                            1

Finished Synthesys Starting PnR with NextPnR Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5 Packing constants.. Packing Shadow RAM.. Packing GSR.. Packing IOs.. Packing diff IOs.. Packing IO logic.. Packing wide LUTs.. Packing LUT5s.. Packing LUT6s.. Packing LUT7s.. Packing LUT8s.. Packing ALUs.. Packing LUT-FFs.. Packing non-LUT FFs.. Packing PLLs.. Checksum: 0x77743ab0 Annotating ports with timing budgets for target frequency 27.00 MHz Checksum: 0x77743ab0 Placed 7 cells based on constraints. Creating initial analytic placement for 71 cells, random placement wirelen = 2954. Running main analytical placer, max placement attempts per cell = 10512. HeAP Placer Time: 0.14s Running simulated annealing placer for refinement. SA placement time 0.10s Max frequency for clock 'clk_IBUF_I_O': 179.99 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 7.56 ns Checksum: 0xdbf4f580 Find global nets... Routing globals... Routing.. Setting up routing queue. Routing 603 arcs. Routing complete. Router1 time 2.15s Checksum: 0x29a9a997 Max frequency for clock 'clk_IBUF_I_O': 213.27 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 5.65 ns Program finished normally.

Device Utilisation:
    VCC:               1/    1   100%
    SLICE:           190/ 8640     2%
    IOB:               7/  274     2%
    ODDR:              0/  274     0%
    MUX2_LUT5:        60/ 4320     1%
    MUX2_LUT6:        30/ 2160     1%
    MUX2_LUT7:         0/ 1080     0%
    MUX2_LUT8:         0/ 1056     0%
    GND:               1/    1   100%
    RAMW:              0/  270     0%
    GSR:               1/    1   100%
    OSC:               0/    1     0%
    rPLL:              0/    2     0%

Finished PnR Starting Bitstream Generation with Apicula testing. You are advised not to use it for production.

Finished Bitstream Generation Starting FPGA Programming with OpenFPGALoader write to flash Jtag frequency : requested 6.00MHz found 1 devices index 0: idcode 0x100481b manufacturer Gowin family GW1N model GW1N(R)-9C irlength 8 File type : fs Parse file Parse c:\Users\phosp\FPGA\FPGA\FPGA.fs: checksum 0xce32 Done DONE bitstream header infos CRCCheck: ON Compress: OFF ConfDataLength: 712 ProgramDoneBypass: OFF SPIAddr: 00fff000 SecurityBit: ON idcode: 1100481b loading_rate: 0 Jtag frequency : requested 2.50MHz Done erase Flash Done Flash Written Done Error: Error key checkSum not found CRC check: Success displayReadReg 0001f020 Memory Erase Gowin VLD Done Final Security Final Ready POR Finished FPGA Programming Toolchain Completed

[lesley-byte]

windows 10 and who knows what else fixed the problem. probably not an issue but more about my level of understanding.