Open trey-sygnalauto opened 6 months ago
You should change it to uboot
How can I try that? I have try inputting all kinds of characters over the serial terminal during boot.
I thought it wrote that, wasn't it ctrl+C?
It did write that to the terminal during boot. Holding Ctrl+C during boot does nothing. It appears they may have locked down this new firmware.
I'm working on getting access to a Nokia XS-010X-Q via the serial port. Upon connection I can watch the device go through boot, but then it looks like the device turns off its serial port. Active firmware reported in webgui is 3FE49337BOCK28, standby FW is 3FE49337AOCK80. Do we know if there is a pad we can short to force boot into the other image?
`CE: BL1: OTP Clock Speed 62 MHz NOTICE: BL1: CPU Clock Speed 666 MHz NOTICE: BL1: I/O Clock 100 MHz NOTICE: BL1: PER Clock 125 MHz NOTICE: Secure Boot Firmware - Cortina Access Inc. NOTICE: BL1: v1.3(release):957a6b2 NOTICE: BL1: Built : 16:43:43, Apr 17 2018 NOTICE: boot from serial NAND flash NOTICE: SERIAL_NAND: ID: 0xaaef00 NOTICE: SERIAL_NAND: chip_id Unknown (use 2Gb) NOTICE: SERIAL_NAND: Sizes - oob 0x40, page 0x800, block 0x20000 ERROR: SERIAL_NAND: flash_get_nand_block_info(848): OTP Status :0x18 != 0x10 ? NOTICE: Platform initialized NOTICE: BL1: Booting BL2 NOTICE: Chip Sub-Revision D
NOTICE: Saturn Soc NOTICE: Change IO clock NOTICE: DIAGNOSTIC_TASK ON NOTICE: DDR3 800MHz NOTICE: PAD_BUS_0=0x5dd80000 NOTICE: PAD_CTRL_PROG=0xc000000 NOTICE: rzq_480code:0x9 NOTICE: # PAD_ZCTRL_STATUS: 0x800a8586 ==> NOTICE: TTCN[TTFN]=0x5[0x0]; [CPMSB,TTCP][TTFP]=0x0,0x5[0x1] NOTICE: # PAD_ZCTRL_STATUS: 0x80091286 ==> NOTICE: TTCN[TTFN]=0x2[0x1]; [CPMSB,TTCP][TTFP]=0x0,0x2[0x1] NOTICE: WriteLeveling PI of DRAM_CK moved 1 tick NOTICE: ddr_write_leveling: 0 NOTICE: ddr_write_leveling: 1 NOTICE: ddr_ck_training:DIAG_ID=2: PLL_PI0 starting value 0x1010301 NOTICE: ddr_ck_training:DIAG_ID=2: PLL_PI1 starting value 0x50808 NOTICE: ddr_ck_training:FREQ=800; DIAG_ID=2: going left 14 ticks; going right 14 ticks NOTICE: ddr_wr_data_training: min_reg_pi_dq[0]: 3; max_reg_pi_dq[0]: 13 NOTICE: ddr_ck_training:DIAG_ID=3: PLL_PI0 starting value 0x1010301 NOTICE: ddr_ck_training:DIAG_ID=3: PLL_PI1 starting value 0x50707 NOTICE: ddr_ck_training:FREQ=800; DIAG_ID=3: going left 14 ticks; going right 14 ticks NOTICE: ddr_dqs_gating: dqs_en gating trained as: 2 NOTICE: ddr_dqs_gating: dqs_en gating trained as: 2 NOTICE: ddr_ck_training:DIAG_ID=4: PLL_PI0 starting value 0x1010301 NOTICE: ddr_ck_training:DIAG_ID=4: PLL_PI1 starting value 0x50707 NOTICE: ddr_ck_training:FREQ=800; DIAG_ID=4: going left 14 ticks; going right 15 ticks NOTICE: rising_dqs_in_dly[0]: 0~31=15 NOTICE: rising_dqs_in_dly[1]: 0~31=15 NOTICE: rising_dqs_in_dly[2]: 0~31=15 NOTICE: rising_dqs_in_dly[3]: 0~31=15 NOTICE: falling_dqs_in_dly[0]:0~31=15 NOTICE: falling_dqs_in_dly[1]:0~31=15 NOTICE: falling_dqs_in_dly[2]:0~31=15 NOTICE: falling_dqs_in_dly[3]:0~31=15 NOTICE: rising_dqs_in_dly[4]: 0~31=15 NOTICE: rising_dqs_in_dly[5]: 1~31=16 NOTICE: rising_dqs_in_dly[6]: 0~31=15 NOTICE: rising_dqs_in_dly[7]: 0~31=15 NOTICE: falling_dqs_in_dly[4]:0~31=15 NOTICE: falling_dqs_in_dly[5]:0~31=15 NOTICE: falling_dqs_in_dly[6]:0~31=15 NOTICE: falling_dqs_in_dly[7]:0~31=15 NOTICE: rising_dqs_in_dly[8]: 1~31=16 NOTICE: rising_dqs_in_dly[9]: 0~31=15 NOTICE: rising_dqs_in_dly[10]: 1~31=16 NOTICE: rising_dqs_in_dly[11]: 0~31=15 NOTICE: falling_dqs_in_dly[8]:0~31=15 NOTICE: falling_dqs_in_dly[9]:0~31=15 NOTICE: falling_dqs_in_dly[10]:0~31=15 NOTICE: falling_dqs_in_dly[11]:0~31=15 NOTICE: rising_dqs_in_dly[12]: 0~31=15 NOTICE: rising_dqs_in_dly[13]: 0~31=15 NOTICE: rising_dqs_in_dly[14]: 0~31=15 NOTICE: rising_dqs_in_dly[15]: 0~31=15 NOTICE: falling_dqs_in_dly[12]:0~31=15 NOTICE: falling_dqs_in_dly[13]:0~31=15 NOTICE: falling_dqs_in_dly[14]:0~31=15 NOTICE: falling_dqs_in_dly[15]:0~31=15 NOTICE: ddr_ck_training:DIAG_ID=5: PLL_PI0 starting value 0x1010301 NOTICE: ddr_ck_training:DIAG_ID=5: PLL_PI1 starting value 0x50707 NOTICE: ddr_ck_training:FREQ=800; DIAG_ID=5: going left 14 ticks; going right 15 ticks NOTICE: DDR Size: 128MB NOTICE: Start DDR scan ... NOTICE: DDR scan done NOTICE: DDR Init done... NOTICE: Recover io_clk... NOTICE: Reduce Power for SFU NOTICE: boot from serial NAND flash NOTICE: SERIAL_NAND: ID: 0xaaef00 NOTICE: SERIAL_NAND: chip_id Unknown (use 2Gb) NOTICE: SERIAL_NAND: Sizes - oob 0x40, page 0x800, block 0x20000 ERROR: SERIAL_NAND: flash_get_nand_block_info(848): OTP Status :0x18 != 0x10 ? NOTICE: BL2: v1.3(release):0e4fa4b NOTICE: BL2: Built : 08:52:24, Jun 29 2020
U-Boot 2015.04 (Aug 22 2022 - 14:54:39) Saturn-ASIC CIG XGS-PON Boot Version: 1.0.0
DRAM: 128 MiB SPI NAND: W25N01GV (0xefaa21) spare: 0x40 (64B) page: 0x800 (2KB) block: 0x20000 (128KB) chip: 0x8000000(128MB) Mode: Q/4 SPI NAND: W25N01GV (0xefaa21) spare: 0x40 (64B) page: 0x800 (2KB) block: 0x20000 (128KB) chip: 0x8000000(128MB) Mode: Q/4 crc1,2 ret is 0 0 value is 0xc15b2fe 0xc15b2fe,flag is 1 1 To detect 5s reset.(185) To detect 5s reset end.(186) SPI NAND: W25N01GV (0xefaa21) spare: 0x40 (64B) page: 0x800 (2KB) block: 0x20000 (128KB) chip: 0x8000000(128MB) Mode: Q/4 done Valid environment: 2 done Valid environment: 1 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Of course the periods all are hex 0x00 and no prompt is ever displayed.