MT29F2G01ABA这个芯片可否？

[xlxlxll]

想用K2P试试这个功能，不知道这个spi nand芯片能不能成功。PDFN8封装的1gb/2gb芯片不好找，看了看也就这个还行。

[hackpascal]

datasheet上面如果写了SPI NOR Read Configuration就可以

[xlxlxll]

SPI NOR Read Configuration Some chipset vendors may have already designed in SPI NOR IP to support system boot; address allocation on clock cycle in SPI NAND read from cache protocol will cause incompatibility. To be drop-incompatible to SPI NOR read protocol, this device offers an alternative solution to implement 03h/0Bh commands, as are done with SPI NOR. Refer to the Electrical Specifications for detail timing requirement. This solution would be enabled using the following command sequence: • SET FEATURE command (1Fh) with feature address B0h and CFG bits[2:0] = 101b (access SPI NOR read protocol enable mode) • WRITE ENABLE command (06h) • PROGRAM EXECUTE command (10h) with block/page address all 0 • GET FEATURE command (0Fh) with status register address C0h to check until device is ready (OIP bit clear) and verify that P_FAIL bit is not set • SET FEATURE command (1Fh) with feature address B0h and CFG bits[2:0] = 000b (return to normal operation mode) • GET FEATURE command (0Fh) at address B0h and CFG bits[2:0] = 101b to verify all 0; all 1 indicates SPI NOR mode not enabled. It is a nonvolatile configuration setting and power cycle will not recover it back to SPI NAND default mode. The rest of the SPI NAND commands still work in this configuration.