halftop / halftop.github.io

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Verilog没有葵花宝典——day2(门电路) | 1/2顶点 #9

Open halftop opened 5 years ago

halftop commented 5 years ago

https://halftop.github.io/post/verilog-day2/

有输入有输出,才是正确的学习方式。