Does this support RISC-V Vector Extension

[DmitriLyalikov]

Hi,

I am absolutely new to this environment and am exploring if this can help me in an image processing program (canny edge detector) targeting the RISC-V vector instruction set, particularly the Hwacha Vector accelerator. Does/Will this support development for this architecure? If so, how/what should I know about doing something like this. I currently have a benchmark C program, and i am wondering if instead of converting this to the RISC-V Vector assembly, this tool can aid in this development some way.

Thanks for your advice

-Dmitri

[steven-johnson]

Yes, we support the RISC-V vector instruction set, though this support is still relatively new, and (mostly) relies on LLVM's RISC-V backend at this point -- it's entirely possible that there are glitches that will be worked out over time.

To use it, I recommend using top-of-tree LLVM (I'm not sure if LLVM16 has good enough support or not -- it might, but I haven't tested it); you'll need to specify a Halide target string like riscv-64-$OS-rvv-vector_bits_$N, where $OS is the operating system you are targeting (e.g. linux, android) and $N is the bit width of the vector registers (e.g., 128).