Makefile issues need to be fixed

[GoogleCodeExporter]

Makefile has two issues:

1. It shojuldn't call 'make' directly, instead it should call $(MAKE). $(MAKE) 
will be expanded to whatever make utility is used, and it isn't always just 
'make'

2. It shouldn't have the line CC=gcc. CC is automatically substituted by make 
to the default compiler on the system. There is no need to set it explicitly.

Original issue reported on code.google.com by yuriv...@gmail.com on 6 Feb 2014 at 10:18

[GoogleCodeExporter]

OK for point 1

Original comment by yann.col...@gmail.com on 6 Feb 2014 at 10:22

• Changed state: Accepted

[GoogleCodeExporter]

For point 2 (regarding CC), 
I would need a link to a documentation which state your recommendation 
regarding CC usage,
and then some test to validate it works in real life environment.

Regards

Original comment by yann.col...@gmail.com on 6 Feb 2014 at 10:25

[GoogleCodeExporter]

All gmake tutorials say this, here for example it says that $(CC) is in an 
implicit rule to compile C:
http://www.tutorialspoint.com/makefile/makefile_macros.htm

Also here is how your Makefile was ported to FreeBSD:
https://svn0.us-west.freebsd.org/ports/head/archivers/lz4/files/patch-Makefile

Original comment by yuriv...@gmail.com on 6 Feb 2014 at 11:10

[GoogleCodeExporter]

OK, thanks for the links and detailed instructions.

Another question :
what is the purpose of this line :
CC:=$(CC)

Isn't it the same as no line at all ?

Original comment by yann.col...@gmail.com on 27 Feb 2014 at 8:28

[GoogleCodeExporter]

Fixed into r114

Original comment by yann.col...@gmail.com on 12 Mar 2014 at 2:57

• Changed state: Fixed