search

harshbhosale01 / image-processing-fpga

Image processing on FPGA using verilog
MIT License
20 stars 1 forks source link

README Empty Link #2

Open oguzkpasa opened 1 year ago

oguzkpasa commented 1 year ago

There is a empty link in README - Open Tang Dynasty and generate RTL file by creating project and following [this process](). Could you fix that? Thanks in advance.

harshbhosale01 commented 1 year ago

@oguzkpasa This README needs to be updated, it will take time. But if you want to replicate this project or have some queries, connect with me on mail

oguzkpasa commented 1 year ago

Hello, First of all thanks for your feedback. I am a Electronics & Communication Engineering student. I have a thesis about JPEG Compression project in FPGA so I am searching open source JPEG Compression IP. I found your repo. My thesis is about getting data from OV7670 Camera (which is i finished before) and make compression process and sending ethernet via FPGA. My question is, is there a block design of your IP running in real time?

harsh @.***>, 25 Mar 2023 Cmt, 10:12 tarihinde şunu yazdı:

@oguzkpasa https://github.com/oguzkpasa This README needs to be updated, it will take time. But if you want to replicate this project or have some queries, connect with me on mail @.***>

— Reply to this email directly, view it on GitHub https://github.com/harshbhosale01/image-processing-fpga/issues/2#issuecomment-1483749032, or unsubscribe https://github.com/notifications/unsubscribe-auth/AV5HJKNBQKBPLVQKWKKMDJ3W52LFLANCNFSM6AAAAAAWA6ELBY . You are receiving this because you were mentioned.Message ID: @.***>

oguzkpasa commented 1 year ago

PS: Im using Zybo Z7-20 board.

Oğuz Kaan Paşa @.***>, 25 Mar 2023 Cmt, 12:44 tarihinde şunu yazdı:

Hello, First of all thanks for your feedback. I am a Electronics & Communication Engineering student. I have a thesis about JPEG Compression project in FPGA so I am searching open source JPEG Compression IP. I found your repo. My thesis is about getting data from OV7670 Camera (which is i finished before) and make compression process and sending ethernet via FPGA. My question is, is there a block design of your IP running in real time?

harsh @.***>, 25 Mar 2023 Cmt, 10:12 tarihinde şunu yazdı:

@oguzkpasa https://github.com/oguzkpasa This README needs to be updated, it will take time. But if you want to replicate this project or have some queries, connect with me on mail @.***>

— Reply to this email directly, view it on GitHub https://github.com/harshbhosale01/image-processing-fpga/issues/2#issuecomment-1483749032, or unsubscribe https://github.com/notifications/unsubscribe-auth/AV5HJKNBQKBPLVQKWKKMDJ3W52LFLANCNFSM6AAAAAAWA6ELBY . You are receiving this because you were mentioned.Message ID: @.***>