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harvard-acc / gem5-aladdin

End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
BSD 3-Clause "New" or "Revised" License
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Is gem5-aladdin okay in simulating systolic arrays? #10

Open zhaohan-xi opened 5 years ago

zhaohan-xi commented 5 years ago

I hope that systolic array is not a strange name nowadays. I see a lot of custom accelerators (like TPU) use systolic array as very crucial part in their design. Therefore, I wonder is Gem5-Aladdin eligible to build such a systolic array-based accelerator? And then fetching data from surrounding buffer to feed into this accelerator as a specific dataflow?

Of course, my final target is interaction analysis between this accelerator and surrounding component, not internal NoC issues...

xyzsam commented 5 years ago

There's two parts of your question: can Aladdin be used to model a systolic array, and can gem5-aladdin be used to model a systolic array accelerator?

To the first part: In theory it's possible to simulate a systolic array with Aladdin, but it is challenging to represent that sort of parallelism in C, and ultimately that is the primary limitation. I've seen ways to do this in C-based HLS solutions but it's not at all natural or intuitive. It's also likely for Aladdin to have some issues inferring the appropriate data dependencies since we haven't tested such code on it before.

To the second part: gem5-aladdin contributes more than just connecting Aladdin with gem5; it also implements a fairly general interface between a CPU and a coarse-grained accelerator. So if you had a separate transaction-level systolic array accelerator model, it would be really easy to plug that into gem5-Aladdin and invoke it almost exactly as you would with an Aladdin based model. We have some ongoing work in this particular area, so stay tuned...

zhaohan-xi commented 5 years ago

Thanks for @xyzsam in answering previous question! I am a beginner in hardware simulation and the only one aim at accelerator design in our research group. Our advisor suggested me gem5, then I found gem5-aladdin as a specialist that looks closer with my need for on-chip accelerator design.

However, now I am a little questioning whether gem5 or derived tools are eligible in inner functionality design of accelerator, since I have only seen many gem5 works mainly focus on interaction issues among on-chip components. Choosing a suitable simulator is a very significant step after purposing a designing idea. Thus it would be my great appreciation if any instructive suggestion could be given by showing whether gem5 / -aladdin a perfect fit in developing special-purpose accelerator.

xyzsam commented 5 years ago

gem5-aladdin is a good candidate for rapid, high level design exploration of the overall accelerator architecture as well as system interactions - it's not only for system co-design. If you don't have any idea what the accelerator microarchitecture might look like, it's a great way to get started. Once you figure out the major parameters of your accelerator, and you want to explore even lower-level optimization and design, you probably want to move on to RTL.