FPGA reconfiguration at runtime via xdevcfg driver

[lucysrausch]

Hey,

thanks for your work, I will try using it for a future project. You're writing that the fpga bitstream needs to be loaded by the FSBL and I wonder why is it so? I need to reload the fpga bitstream via the xdevcfg driver for different fpga usages. For this, it is fine if the HDMI image is blank for a second or so, but after that it has to recover.

Same for the Sii9022. Is it possible to configure it from linux using /dev/i2c-0 rather than via the FSBL? I have another device on the same I2C bus so I would prefer to initialize them at the same time from my linux application.

Thanks in advance for any help you can give me!

Best, Niklas

[hauerdie]

Hi Niklas,

I found it the easiest way to configure the Video Timing Controller and Video DMA Controller in the FSBL. There I can use Xilinx library functions. But the FPGA needs to be configured before that happens. Therefore I load the bitstream from the FSBL and use the fsbl_hooks.c to start Video Timing and DMA. There shouldn't be any issue by reconfiguration via xdevcfg. Only Video Timing Controller and DMA needs to be started again and of course Si9022, but this can be done via /dev/i2c. Here are the Si9022 registers and values for 1080p60 and some info on the registers.

{0x1e, 0x00},
{0x08, 0x70},
{0x09, 0x00},
{0x0a, 0x00},
{0x60, 0x04},
{0x3c, 0x01},
{0x1a, 0x11},
{0x00, 0x02},   // PixelClock/10000 - LSB
{0x01, 0x3a},   // PixelClock/10000 - MSB
{0x02, 0x70},   // Vertical Frequency in HZ - LSB
{0x03, 0x17},   // Vertical Frequency in HZ - MSB
{0x04, 0x98},   // Total Pixels per line - LSB
{0x05, 0x08},   // Total Pixels per line - MSB
{0x06, 0x65},   // Total Lines - LSB
{0x07, 0x04},   // Total Lines - MSB
{0x08, 0x70},
{0x1a, 0x01},

For starting VTC and VDMA from Linux you can write the registers directly by mapping them to userspace. I used devmem2 for debugging to read and write the registers. Registers and sequence can be found in Xilinx VTC and VDMA Documentation.

I guess you can also use the Xilinx VMDA and VTC Linux drivers. https://github.com/torvalds/linux/tree/master/drivers/media/platform/xilinx I need to have a closer lock into this some time.

Hope this helps, Didi

[lucysrausch]

Thanks a lot for the explanation. I will try this out probably next week.

From my experience, it is sometimes possible to reuse the DMA stream established to the fpga even after a reconfiguration, as long as the addresses don't change. I never tried that for VDMA, but I guess I will find out soon. If is doesn't work I will try out the VDMA drivers.

[hauerdie]

Hi Niklas,

i tried it and it works. After loading the new bitstream, the VTC stopped and the VDMA registers are cleared, so no HDMI output. I just started the VTC and configured the VDMA again and the display went on again. I guess if the screen resolution is still the same, no action on the Sii9020 needs do be done.

Here is the python script I used to start the display again, it uses pydevmem.

import devmem

VDMA_BASE = 0x43000000
VTC_BASE = 0x43c00000

MM2S_VDMACR = 0x00
MM2S_VDMASR = 0x04
MM2S_VSIZE = 0x50
MM2S_HSIZE = 0x54
MM2S_FRMDLY_STRIDE = 0x58
MM2S_START_ADDRESS_1 = 0x5c

XVTC_CTL = 0x00

vdma = devmem.DevMem(VDMA_BASE, 0xF4, "/dev/mem", 0)
vtc = devmem.DevMem(VTC_BASE, 0x0140, "/dev/mem", 0)

vtc.write(XVTC_CTL, [0x00000011])

vdma.write(MM2S_START_ADDRESS_1,[0x3f000000])
vdma.write(MM2S_VDMACR,[0x00018003])
vdma.write(MM2S_HSIZE,[0x00001e00])
vdma.write(MM2S_FRMDLY_STRIDE,[0x00001e00])
vdma.write(MM2S_VSIZE,[0x00000438])

btw: Euren Talk auf der GPN18 fand ich sehr interessant.

[lucysrausch]

Awesome, thanks! This is super helpful, would've taken me hours to get into this. Btw, I just exported the bitstream and noticed that the constants in the Video Timing Controller are set for 720p. Is this correct or should I change it to 1080p?

[hauerdie]

Yes you need to change it. I didn't notice that I changed this also, In the project from myirtech its set to 720p. In the fsbl I just start the vtc with the constants from the project, so thats an issue. Thanks

[lucysrausch]

Hello again, today I finally had access to my z-turn board again and I managed to get both HDMI out at boot and reloading a bitstream at runtime working perfectly. Thank you very much for the support!

PS: Bist du beim 35c3? Dann kann ich dir mal zeigen, wofür ich das alles brauche ^^

[lucysrausch]

This is not directly related to the original question, but it might fit in here as well because it is probably related to the VDMA register config:

The VDMA read works perfectly fine, however for my application I need a VDMA write as well. For this, I need to expand the axi_mem_interconnect to expose two AXI slaves.

However when I do this, the VDMA read stops working and I get no HDMI output. For debugging I tried changing nothing but this parameter, with a single S00_AXI everything works.

I am not exactly sure why this happens, I never had a problem with extending AXI interconnects. Do you have an idea what could cause this problem?

Thanks!

[hauerdie]

Hi, I never treid VDMA write. But recently I acquired a Zynqberry, in the example files it also uses VDMA for HDMI out and additionally VDMA write for reading a stream from a CSI camera. Hadn’t had time to try it, but you can find the reference designs in the download area of trenz electronic.

Did you check the VDMA registers, the status register should reflect why the read DMA stopped.