use altlvds_tx + oserdes2 to drive TMDS

[sameer]

This should produce a higher quality HDMI signal.

Derived from altlvds contribution by @nockieboy and BrianHG https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/

Breaking changes and user action required:

• Fast clock (clk_pixel_x10) renamed to clk_pixel_x5 and will always be DDR (5x as fast as clk pixel instead of 10x)
  • 10x multiplier in PLL must be changed to 5x
• tmds_p/tmds_n, tmds_clock_p/tmds_clock_n renamed to tmds and tmds_clock respectively
  • Intel/Altera users: the negated component will be automatically generated by Quartus so just remove explicit declaration of that
  • Xilinx users must instantiate an OBUFDS on top of the HDMI entity for each of the 3 tmds lines + the tmds clock
  • Unfortunately there is no equivalent for Quartus auto-generation behavior as far as I've seen