sameer
commented
3 years ago Hey, thanks for bringing this to my attention. I was not aware that SystemVerilog wouldn't work for Spartan 6. I'm most familiar with Quartus and Intel since that's what was available at my university, but I recently got a Spartan 7 to help test with 🙂
The project was originally in Verilog so it shouldn't be too much work to convert it back. The mixed packed/unpacked assignments look tricky. The best way to handle them is flattening i.e. [2442-1:0] for audio sample word packet.
I will look into some conversion tools to see if there's an option there. I can't revert all the projects under hdl-util back to Verilog, but since this is the most used project in the org it might be valuable to offer it as a legacy option. Though support for that would not be guaranteed in the long term.
Will get back to you once I have more information.
On Fri, Apr 2, 2021, at 00:01, Antonio Sanchez wrote:
I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog. Vivado supports SV but not Spartan 6 family :-( I tried to translate this code to Verilog but packed assignaments like this get me confussed and don't know how to do it. Any clue to translate it? Is there any tool to convert it to Verilog? Thanks.
logic [23:0] audio_sample_word_packet [3:0] [1:0];...
logic [23:0] audio_sample_word_buffer [1:0] [3:0] [1:0];...
audio_sample_word_packet <= audio_sample_word_buffer[!sample_buffer_current];
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TheSonders
I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog. Vivado supports SV but not Spartan 6 family :-( I tried to translate this code to Verilog but packed assignaments like this get me confussed and don't know how to do it. Any clue to translate it? Is there any tool to convert it to Verilog? Thanks.
_logic [23:0] audio_sample_wordpacket [3:0] [1:0];...
_logic [23:0] audio_sample_wordbuffer [1:0] [3:0] [1:0];...
_audio_sample_word_packet <= audio_sample_word_buffer[!sample_buffercurrent];