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hdl-util / hdmi

Send video/audio over HDMI on an FPGA
https://purisa.me/blog/hdmi-released/
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IP-less serializer is not working #37

Open leduchuybk opened 1 year ago

leduchuybk commented 1 year ago

At serializer.v line 275, i found that signals tmds and tmds_clock are driven by mutiple signals. It made code unsynthesised and wrong simulation. It would be helpful if you post your algorithm about this seder

muzhiyun commented 1 year ago

I had this problem today.In fact, someone else has already asked this question https://github.com/hdl-util/hdmi/issues/33 , I use Tang Nano 9K and System Verilog 2017 like Apuder , so I guess maybe you are also using Gowin or even Lichee Tang Nano?

It seems that the author had knew about the problem through the previous issue, and Apuder provided a patch in that issue. Although the hyperlink is currently inaccessible, the modified file can still be found from https://github.com/apuder/TRS-IO/blob/nano-9k-xray/src/fpga/vg/v2.0/TRS-IO/src/hdmi/serializer.sv.

Through simple comparison, I concluded two points:

  1. Apuder added define GOWINSEMImacro to solve this problem.
  2. Zwenergy submitted the modification to https://github.com/hdl-util/hdmi/pull/34 , and added the elsif GW_IDE macro in the serializer.sv file.

Therefore, I think adding define GW_IDE to the first line of the serializer.sv file can make the modification of Zwenergy take effect.In fact , the error has been successfully resolved as I supposed.

If you also use Gowin, can you try the method ?

@leduchuybk