hdl-util / hdmi

Send video/audio over HDMI on an FPGA
https://purisa.me/blog/hdmi-released/
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fixes #43: enforce hdmi 12px minimum control period during video and data-island preambles #44

Closed krisdover closed 10 months ago

krisdover commented 10 months ago

Also fixes off-by-one errors on VG, VP, and VSync. I'm running some of this code on a Tang Nano 4K and after hooking it up to a logic analyzer and inspecting the pre-TMDS encoded signals, I noticed the VSync was delayed by an extra video line, and also VG and VP were being generated at the end of the last active video line.