Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
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Add a `additional_inputs=...` or similar to `verilator_cc_library` #354
Some verilog code, such as the serv core, uses $readmemh to read memory content to pre-fill memory arrays. This apparently happens at verilation step, making it necessary to provide the memory file to the verilator_cc_library rule at compile time.
While it is possible to provide additional files to verilator_library, such files become part of the runfiles, and are not available at build time.
Some verilog code, such as the
servcore, uses$readmemhto read memory content to pre-fill memory arrays. This apparently happens at verilation step, making it necessary to provide the memory file to theverilator_cc_libraryrule at compile time.While it is possible to provide additional files to
verilator_library, such files become part of therunfiles, and are not available at build time.