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hdl / containers

Building and deploying container images for open source electronic design automation (EDA)
https://hdl.github.io/containers/
Apache License 2.0
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Add Verible #57

Closed patrickrst closed 1 year ago

patrickrst commented 2 years ago

Hello! Here's a Dockerfile for Verible set of tools. I wasn't sure what to do for the test and neither how to update the doc, so looking for guidance.

Related chipsalliance/verible#1303

patrickrst commented 2 years ago

It's neither "sim", "synth", "impl", "formal" or "asic", is it?

Maybe we need a new category such as "static code analysis" or "dev tools", or more specific categories like "linting" and "formatting" tools.

umarcor commented 2 years ago

@patrickrst categories are not "strict". E.g. GHDL allows sim, synth and linting. Let's put Verilog in graph "F4PGA" for now, since both are under the umbrella of the CHIPS Alliance. Do you want to give a try at updating the graphs or shall I take care of it?

patrickrst commented 2 years ago

Sorry forgot to reply. I update the graph, you can have a look when you have time