issues
search
hdl
/
pyHDLParser
Simple Python parser for extracting HDL (VHDL or Verilog) documentation
https://HDL.github.io/pyHDLParser
MIT License
17
stars
10
forks
source link
fix VhdlExtractor.is_array + use setup.cfg + clean
#10
Open
kammoh
opened
2 years ago
kammoh
commented
2 years ago
start using setup.cfg
fix VhdlExtractor.is_array (used in symbulator) which was completely broken
avoid adding log handler (unless no handlers already exist), to avoid messing up caller's logger.
verilog_parser: more rebust endmodule identification
fix identification of file extension (e.g. my.module.v)
consider '.sv' file extension as (System)Verilog