VHDL parser from andres manelli's fork for entity parsing support

[michael-etzkorn]

This mirrors the pull request here https://github.com/kevinpt/hdlparse/pull/14 using the master branch of https://github.com/andresmanelli/hdlparse . I've briefly tested this with capstone.vhd from https://github.com/stnolting/captouch . It only seems to pick up the out_filter_t type, but at least it does some sort of parsing of the entity.

>> import hdlparse.vhdl_parser as vhdl
>> vhdl_ex = vhdl.VhdlExtractor()
>> vhdl_objs = vhdl_ex.extract_objects("captouch.vhd")
>> vhdl_objs
[VhdlEntity('captouch'), VhdlType('out_filter_t', 'array_type')]
>> import pprint
>> pprint.pprint(vhdl_objs[0].__dict__) 
{'desc': [],
 'generics': [VhdlParameter('F_CLOCK', 'in', 'integer'),
              VhdlParameter('NUM_PADS', 'in', 'integer'),
              VhdlParameter('SENSITIVITY', 'in', 'integer')],
 'kind': 'entity',
 'name': 'captouch',
 'ports': [VhdlParameter('clk_i', 'in', 'std_ulogic'),
           VhdlParameter('rstn_i', 'in', 'std_ulogic'),
           VhdlParameter('rstn_sync_i', 'in', 'std_ulogic'),
           VhdlParameter('ready_o', 'out', 'std_ulogic'),
           VhdlParameter('touch_o', 'out', 'std_ulogic_vector(NUM_PADS-1 downto 0)'),
           VhdlParameter('pad_io', 'inout', 'std_logic_vector(NUM_PADS-1 downto 0)')],
 'sections': {}}

Previous behavior: vhdl_objs would return as an empty list.

I didn't go through and reapply @andresmanelli's changes. Instead, I just patched the branch with his vhdl_parser.py so @vvvverre's format changes would have to be redone.

[andresmanelli]

If you apply this change:

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index af9789d..05e424c 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -94,6 +94,7 @@ vhdl_tokens = {
   'architecture': [
     (r'end\s+\w+\s*;', 'end_arch', '#pop'),
     (r'/\*', 'block_comment', 'block_comment'),
+    (r'type\s+(\w+)\s*is', 'type', 'type_decl'),
     (r'--.*\n', None),
   ],
   'generic_list': [

you get:

In [1]: import hdlparse.vhdl_parser as vhdl
In [2]: vhdl_ex = vhdl.VhdlExtractor()
In [3]: vhdl_objs = vhdl_ex.extract_objects("captouch.vhd")
In [4]: vhdl_objs
Out[4]:
[VhdlEntity('captouch'),
 VhdlType('ctrl_state_t', 'enum_type'),
 VhdlType('ctrl_t', 'record_type'),
 VhdlType('out_filter_t', 'array_type')]

It's strange that you got one type at all, because the type parser was declared at the root and package level. I added the same line at the architecture level .

[michael-etzkorn]

Hi Andres, I've pushed your fix for type parsing to this branch. Hopefully this weekend I can reintroduce vvvverre's style changes so the style is consistent between the two parsers.

I'm also in favor of parsing the logic type for systemverilog so I'll introduce a PR for that soon (even if this python parser isn't intended to be a full blown SV parser. It'll be nice to have some of the basics.)

[andresmanelli]

I'm not sure if that should be included in another file ? (another parser for SV). But other than that this PR LGTM.

I'll approve, waiting for another reviewer before merge.

[Paebbels]

@umarcor this PR looks ready to be merged. Any objections?

[Paebbels]

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