Open vvvverre opened 2 years ago
I forgot to mention I have a branch in my fork with the potential solutions I mentioned above, in case anyone would like to test them: https://github.com/vvvverre/pyHDLParser/tree/fix_component_in_entity
I also just realised the code for handling architectures has the same bug:
@@ -92,7 +99,7 @@ vhdl_tokens = {
(r'--.*\n', None),
],
'architecture': [
- (r'end\s+\w+\s*;', 'end_arch', '#pop'),
+ (r'end\s+(architecture\s+)?\w+\s*;', 'end_arch', '#pop'),
(r'/\*', 'block_comment', 'block_comment'),
(r'type\s+(\w+)\s*is', 'type', 'type_decl'),
(r'component\s+(\w+)\s*is', 'component', 'component'),
@vvvverre maybe you can create a PR from branch fix_component_in_entity, and add the code example above as a test file?
This bug was passed to me by someone else, but I am posting it as an issue so we can track it.
Currently pyHDLparser does not parse component declarations inside the architecture of an entity correctly. I have attached below a simple example of a VHDL file that recreates this bug.
I used the following python code to recreate the bugs.
The output I would expect for this is as follows:
Instead the output is as follows:
There are two issues here:
full_adder
is never recognizedfull_adder
component are added to the ports of the entityI believe the first issue is caused by an incorrect regex, which would only trigger on the syntax
end three_bit_adder;
but notend entity three_bit_adder;
. I think this can be fixed like this:This changes the output to:
Which is more correct, but still misses the component declaration. Adding the following token gives the expected output:
One outstanding question I have is whether there should be some way of indicating that the VHDL component is declared inside the architecture?