Vivado version compatibilty

[fpgasdr]

Hello,

what version is used of Vivado is used?.

have tried to compile the design with Vivado 2017.4 but got some syntax errors in Sytem Verilog code and i guess could be the Vivado version.

Thanks!

[hellgate202]

Hi, can you please attach error messages from your Vivado output? I was using Vivado 2018.3

[fpgasdr]

Hello,

first tried with vivado 2017.4 in one computer and get a compilation error in the line_extender.sv

output_reg <= $bits( axi4_stream_word_t )(' 0 );

The error was:

_[Synth 8-2715] syntax error near ' ["/Vivado/PandaCam/example/pandacam.srcs/sources_1/bd/pandacam/ipshared/frame_extender/src/lineextender.sv":43]

The error line is: output_reg <= $bits( axi4_stream_word_t )'( 0 );

This error is solved if I compile the code with vivado 2018.2 so my guess is some systemverilog incompatibilities due older vivado

But the error I can't solve with vivado 2018.2 is the testbench for the csi, the tb_csi.sv file, and don't know if this could be the same problem or not. so I'm asking before install a newer version of Vivado.

_ERROR: [VRFC 10-395] cannot assign an unpacked type to a packed type [/Vivado/PandaCam/ip/csi2_rx/tb/../lib/axi4_lib/src/class/AXI4StreamSlave.sv:154] ERROR: [VRFC 10-395] cannot assign a packed type to an unpacked type [/wrk/xhdhdnobkup2/mounicav/xsimsource/xsimHEAD/data/verilog/src/std.sv:72]

The line in the first error is the next one:

rx_data_mbx.put( rx_byte_q );

the other file is missing...

[hellgate202]

I run testbenches in QuestaSim, I'm not sure Vivado Simulator can handle SV features I was using there. I also do not think this testbench is up-to-date with IMX477. But in order to try, you can try to run it in free version of ModelSim. Launch it and then execute do path_to_make.tcl_in_tb_folder You will probably fail to do it because ModelSim doesn't support vopt command I use in make.tcl script to fix it change this vopt +acc tb_csi2 -L unisim -o tb_csi2_opt vsim tb_csi2_opt to this vsim -L unisim tb_csi2 You must have precompiled Vivado libraries path in Modelsim in order to run it, this can be googled.

[fpgasdr]

Thanks for your support. yes, I didn't realize you simulate design with Questa.