A General Question on TLB Flush in seL4

heshamelmatary / seL4-riscv-mk

seL4 microkernel RISC-V port (OUTDATED!)

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A General Question on TLB Flush in seL4 #2

Closed zhanghongce closed 7 years ago

zhanghongce commented 7 years ago

Hi, I just wonder what is the current situation of running seL4 on Rocket chip. Spike simulator does TLB flush more often than the Rocket chip. The latter only performs that on "sfence.vm" instructions.

I'm new to this repo, and may not find the exact memory management code in it. But it seems to me that the TLB flush instruction has not been invoked anywhere in the code. I guess this might be a problem if you port seL4 from spike to Rocket chip. Please correct me if I'm wrong.

Thanks!

heshamelmatary commented 7 years ago

This repo is outdated. I've been working on a more mature/stable version with more features and bug fixes. Please see the latest 2 blog posts for updates.

In brief, and to answer your question, this repo doesn't do TLB operations. But the one in the blog post does, using sfence.vma instruction (RISC-V priv-1.10). If you've any more issues, please report it on the up-to-date repo here.