Pipelined Implementation of MIPS in Verilog

hesitateYU / pipelined-mips-cpu

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Pipelined Implementation of MIPS in Verilog #1

Open GoogleCodeExporter opened 8 years ago

GoogleCodeExporter commented 8 years ago

How to we implement the inter stage registers?
i.e IF/ID, ID/EX, EX/MEM, MEM/WB

In my view we can define them as type reg [:].
The store relevant outputs from previous stages in specific bit positions.

Any suggestions are welcome.

I am using iVerilog over Ubuntu.
And gtkwave to check the simulations

Original issue reported on code.google.com by harte...@gmail.com on 20 Mar 2012 at 5:29

GoogleCodeExporter commented 8 years ago

uh, I simulate the mips code well, then I have to wirte the file 
"instruction.txt" to see the result

Original comment by bg2...@gmail.com on 13 Jan 2013 at 2:40