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heymesut / SJTU_microe

A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
BSD 3-Clause "New" or "Revised" License
28 stars 4 forks source link

BIT GENERATION FAILED #1

Open naveenae opened 2 years ago

naveenae commented 2 years ago

Hi authors,

I was trying to replicate your design. I was able to export an IP from HLS 2019.2 and in Vivado 2019.2 while trying to generate a bitstream, it failed with DRC error [DRC RTSTAT-4] No routable drivers: 2112 net(s) have no routable drivers. The problem bus(es) and/or net(s) are design_1_i/UltraNet_Bypass_0/inst/conv3x3_bn_act_L1_U0/p_2D_PE_array_act_L1_U0/acc_shrink_V_0_7_i_p_1D_PE_array_L1_fu_984/UltraNet_Bypass_mlbW_U74/UltraNet_Bypass_mlbW_DSP48_1_U/p/C[0], ... and (the first 15 of 2112 listed). [DRC RTSTAT-6] Partial route conflicts: 2113 net(s) have a partial conflict. The problem bus(es) and/or net(s) are design_1_i/UltraNet_Bypass_0/inst/conv3x3_bn_act_L1_U0/p_2D_PE_array_act_L1_U0/acc_shrink_V_0_6_i_p_1D_PE_array_L1_fu_975/UltraNet_Bypass_mlbW_U74/UltraNet_Bypass_mlbW_DSP48_1_U/p/C[0], design_1_i/UltraNet_Bypass_0/inst/conv3x3_bn_act_U0/p_2D_PE_array_act_6_U0/grp_p_1D_PE_array_fu_639/UltraNet_Bypass_mPgM_U170/UltraNet_Bypass_mPgM_DSP48_7_U/p/C[0], ... and (the first 15 of 2112 listed), GLOBAL_LOGIC1.

Do you have any suggestions to fix this?

Note: I did not change anything with the design. I just re-ran your whole flow.

Thanks in advance!

heymesut commented 2 years ago

I did not have this problem with Vivado 2019.1. I think this link might help. https://support.xilinx.com/s/question/0D52E00006hptN0SAI/drc-rtstat2-partially-routed-nets-and-drc-rtstat6-partial-route-conflicts?language=en_US