Trained path-level model for timing feature extraction

[Ace-Ma]

Hi, I noticed that in paper a path-level model is required to transfer RTL-stage path to the one in netlist-stage. I wonder if you have such a model in your repository. Thank you.

[kkkkkom8]

Hi, I noticed that in paper a path-level model is required to transfer RTL-stage path to the one in netlist-stage. I wonder if you have such a model in your repository. Thank you.

Same here. I see there is a train_path_rfr.py file, but the data it is referring to is not included in the repo

dc_label_data = f'/data/user/AST_analyzer/ML_model/timing_data/label_all/label_all/label_lst.pkl'
feat_data = f'/data/user/AST_analyzer/ML_model/timing_data/feature/feat_all/feat_all_lst.pkl'

[kkkkkom8]

I went through some issues and comments, so it looks like those data may have copyright issue, so cannot publish.

In case, could you please publish the trained model? Models contain no copyright data, and would make this as a pipe-cleaned repo that is truly functional out of the box.

[fangwenji]

Thanks for your interest in our RTL-stage PPA modeling work. We have enhanced this work to achieve more fine-grained register slack evaluation and more accurate WNS and TNS prediction at the RTL stage, with much easier pre-processing for your own RTL designs. For more details, please refer to RTL-Timer (DAC'24).