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hkust-zhiyao / MasterRTL

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
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FileNotFoundError: [Errno 2] No such file or directory: '/data/user/masterRTL/ML_model/data/label/dc_label_timing.json' #7

Closed Lucas-Wye closed 3 months ago

Lucas-Wye commented 4 months ago

Traceback (most recent call last): File "ML_model/timing/model/xgbooster_regression_kf_tns.py", line 62, in label_data, feat_data = load_data() File "ML_model/timing/model/preprocess.py", line 22, in load_data with open(dc_label_data, "r") as f: FileNotFoundError: [Errno 2] No such file or directory: '/data/user/masterRTL/ML_model/data/label/dc_label_timing.json'

fangwenji commented 3 months ago

The labels are collected after running logic synthesis using Design Compiler. You may replace the label files with your design benchmarks.