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hkust-zhiyao / MasterRTL

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
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FileNotFoundError: [Errno 2] No such file or directory: '/data/user/masterRTL/ML_model/data/label/dc_label_area_pwr.json' #8

Closed Lucas-Wye closed 3 months ago

Lucas-Wye commented 4 months ago

Traceback (most recent call last): File "ML_model/area/model/mix_regression_kf.py", line 117, in label_data, feat_data = load_data_sep() File "ML_model/area/model/preprocess.py", line 46, in load_data_sep with open(dc_label_data, "r") as f: FileNotFoundError: [Errno 2] No such file or directory: '/data/user/masterRTL/ML_model/data/label/dc_label_area_pwr.json'

fangwenji commented 3 months ago

The labels are collected after running logic synthesis using Design Compiler. You may replace the label files with your design benchmarks.

Lucas-Wye commented 3 months ago

The labels are collected after running logic synthesis using Design Compiler. You may replace the label files with your design benchmarks.

thx, but how to generate such a label?

fangwenji commented 3 months ago

It depends on what types of constraints you need to use to generate the target ground-truth PPA. Due to the copyright issue, we could not share our logic synthesis flow using DC. However, you may build up your own flow according to the user manual.

Lucas-Wye commented 3 months ago

It depends on what types of constraints you need to use to generate the target ground-truth PPA. Due to the copyright issue, we could not share our logic synthesis flow using DC. However, you may build up your own flow according to the user manual.

thx, I think I get you points. So the json file is consist of the design name and corresponding PPA, right?

fangwenji commented 3 months ago

Yes, that's correct.