I try to calculate PPA for designs in RTLLM. Following the setting in the paper, I employ DC to conduct logic synthesis.
For timing, I use PT to perform Static Timing Analysis. But I don't know how to get timing for combinational logic circuits like the adder. Can you share some suggestions? Thanks.
I try to calculate PPA for designs in RTLLM. Following the setting in the paper, I employ DC to conduct logic synthesis. For timing, I use PT to perform Static Timing Analysis. But I don't know how to get timing for combinational logic circuits like the adder. Can you share some suggestions? Thanks.