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hneemann / Digital

A digital logic designer and circuit simulator.
GNU General Public License v3.0
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Cannot generate HDL for pin-control with bit-width > 1 #564

Closed holstvoogd closed 3 years ago

holstvoogd commented 3 years ago

I've been working on getting some circuits running on an Arty-A7 board and think I've ran into a bug in the HDL generation.

When I try to generate the HDL, I get a pretty generic error: 'Error during export to VHDL.' I have narrowed it down to having any output connected to a pin control through a splitter. The error and part of the circuit: error

A few observations/notes:

I haven't found any log files or other output to help diagnose the issue further.

hneemann commented 3 years ago

In the simulation, the PinControl component can be used without restrictions. When used in an HDL export, only one pin may be connected to the output. No component is allowed between PinControl and output. Also no splitter. But there should be a better error message.

holstvoogd commented 3 years ago

Ah, makes sense. Thanks for the quick reply!

hneemann commented 3 years ago

@holstvoogd I forgot to mention that for a multi bit output several pin numbers can be given as a comma separated list.

hneemann commented 3 years ago

@holstvoogd If I think about your question, it would be a good opportunity to add a new toolchain configuration that supports the Arty-A7-35/100 boards. Have you already worked on this?

holstvoogd commented 3 years ago

@hneemann Ah, cool. I hadn't considered that, it's perfect for this case.

Yes, I've created a config based of the other digilent board & mapped out part of the I/O. Still have a bunch more pins to do though. I also need to test/debug the clock generation, it seems like the clock on the FPGA runs slower than in simulation.

I'll make a PR when I have the config completed & tested!