Closed sharpie7 closed 2 years ago
On BeebFPGA with SCART output it seems identical to a real Model B.
This is what I'm getting:
The course cursor alignment is controlled by R8 of the 6845 (0, 1 or 2 characters)
The pixel level cursor alignment is just whatever delays there are through the Video Processor
I'm building with IncludeVideoNuLA = true (and have been for a long time)
Which Video Processor are you using?
It's possible this issue only exists with the original Video Processor implementation.
Indeed, this is only an issue with the original Video Processor implementation (IncludeVideoNuLA = false).
This is now fixed.
Hi Again
Question to see whether this is in my port or your original. In Mode 7 the cursor is about 1 or 2 pixels left of where it should be in my MiSTer port. Do you see the same thing?
Do you know where the cursor alignment between the CRTC and the teletext chip is controlled?
Thanks