RISC-V Tube ROM: Write an example of an Illegal Instruction Handler

[hoglet67]

For example, pick one of the simpler instructions from the bit manipulation extension.

e.g. ANDN

https://five-embeddev.com/riscv-bitmanip/draft/bitmanip.html#insns-andn

[hoglet67]

Unfortunately minirv32 decodes ANDN as AND:

This is because it doesn't verify func7 (at the MSB) is 0000000

Nor does the debugger's disassembler:

>> break 10f30
Exec breakpoint set at 10f30
cpu: RISCV debug enable = 1
Exec breakpoint hit at 10f30
00010f30 40007033 and      zero, zero, zero
>> 

[hoglet67]

For reference, here's what I currently have.

This implements opcode 0x77 and shows you can load a register value (in this case ra)

   10 DIM code% 256
   20 FOR I%=0 TO 3 STEP 3
   30 P%=code%
   40 [OPT I%
   50 .align
   60 .install
   70 li a7, &AC000E
   80 li a0, -7
   90 li a1, handler
  100 li a2, 0
  110 ecall
  120 sw a1, oldhandler, t0
  130 ret
  140 :
  150 .oldhandler
  160 equd 0
  170 :
  180 .handler
  190 addi sp, sp, -16
  200 sw t0, 0(sp)
  210 sw t1, 4(sp)
  220 :
  230 csrr t0, mcause
  240 li t1, &00000002 ; Illegal Instruction
  250 bne t0, t1, bail
  260 :
  270 csrr t0, mepc
  280 lw t0, (t0)
  290 li t1, &0000007F
  300 and t0, t0, t1
  310 li t1, &00000077 ; Opcode 0x77 which is undefined
  320 bne t0, t1, bail
  330 :
  340 LI ra, &12345678 ; TODO implement instruction
  350 :
  360 csrr t0, mepc
  370 addi t0, t0, 4
  380 csrw mepc, t0
  390 :
  400 addi sp, sp, 16
  410 lw t0, 0(sp)
  420 lw t0, 4(sp)
  430 :
  440 addi sp, sp, 16
  450 mret
  460 :
  470 .bail
  480 lw t0, 0(sp)
  490 lw t1, 4(sp)
  500 addi sp, sp, 16
  510 lw t0, oldhandler
  520 jalr zero, t0
  530 :
  540 .test
  550 addi sp, sp, -16
  560 sw ra, 0(sp)
  570 EQUD &00000077
  580 mv a0, ra
  590 lw ra, 0(sp)
  600 addi sp, sp, 16
  610 ret
  620 ]
  630 NEXT
  640 CALL install
  650 PRINT ~USR(test)

When run this does:

>RUN
12345678
>