Bare-metal Raspberry Pi project that attaches to the Acorn TUBE interface and emulates many BBC Micro Co Processors
GNU General Public License v3.0
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RISC-V Co Pro: Pass elapsed_us into emulator so that RISC-V timer interrupts work #198
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hoglet67 closed 11 months ago
Currently the emulator is stepped with this call:
elapsedUs is always 0.
This means the timer CSR is never updated:
So it's not possible to use RISC-V timer interrupts.
What's needed here is to somehow map the arm cycle counter register (CCNT) which increments at the ARM clock rate into elapsed_us increments.
Something like:
Then in the main loop of the RISC-V emulator:
I think the above pattern should prevent rounding errors accumulating, though there may be a simpler way!