The problem is the way we have implemented the data transfer loop:
lb t0, R4STATUS(gp) # Test for an pending interrupt signalling end of transfer
bltz t0, Release
lb t0, R3STATUS(gp)
bgez t0, Type1
lb t0, R3DATA(gp)
sb t0, (t2)
addi t2, t2, 1
j Type1
At this point interrupts are disabled, and the loop is only terminated when an R4 interrupt is detected.
At the host side events are handled asynchronous, which means a data transfer can be interrupted by a timer interrupt, and this is immediately propagated to the co processor as a timer event (if enabled) that uses R1.
We don't handle this case: the R1 interrupt is not serviced during the data transfer loop, causing the host to deadlock.
The easiest way to fix this is to re-enable interrupts during the data transfer, which is what is done in the 6809 Tube ROM.
To reproduce this:
The problem is the way we have implemented the data transfer loop:
At this point interrupts are disabled, and the loop is only terminated when an R4 interrupt is detected.
At the host side events are handled asynchronous, which means a data transfer can be interrupted by a timer interrupt, and this is immediately propagated to the co processor as a timer event (if enabled) that uses R1.
We don't handle this case: the R1 interrupt is not serviced during the data transfer loop, causing the host to deadlock.
The easiest way to fix this is to re-enable interrupts during the data transfer, which is what is done in the 6809 Tube ROM.