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hoglet67 / atf15xx_yosys

Design Flow for Atmel/Microchip ATF15xx CPLDs using Yosys and the Atmel Fitter
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Reversed bit order / EDIF in Yosys #2

Closed peterzieba closed 1 year ago

peterzieba commented 1 year ago

Hi,

I came across this which suggests that this might have been fixed but never merged? https://github.com/YosysHQ/yosys/pull/830

This is related to issue #568 and reverse bit order in the generated EDIF.

hoglet67 commented 1 year ago

I'm currently working around this issue with some post-processing of the EDIF in a script: https://github.com/hoglet67/atf15xx_yosys/blob/609d70fe6b26644ff4e91c483dd09c8f2e4f9210/run_yosys.sh#L46

peterzieba commented 1 year ago

I nudged the following ticket https://github.com/YosysHQ/yosys/pull/1489 which ended up getting merged into yosys master.

In theory, one can now do write_edif -lsbidx

I haven't yet had a chance to test this, but I think this might resolve things...

hoglet67 commented 1 year ago

Thanks for nudging this issue Peter. I've just tested the write_edif -lsbidx option and it seems very much equivalent to ugly the perl hack I had in place. The fitter output is identical. So I've updated the run_yosys script to use this option if it's available.