Sometimes the fitter give internal error or unknown cell: id00001 - hints on root cause?

[MattisLind]

Hello!

This is not a bug report for this project, rather a question regarding the Atmel fitters which you might have some input on since you probably have been using them a lot more that I have.

I have fiddled with some code that I tried to fit but I keep getting either of these two errors:

Atmel ATF1508 Fitter Version 1918 (3-21-07)
Copyright 1999,2000 Atmel Corporation

INTERNAL ERROR - Please contact your Hot-Line

Atmel ATF1508 Fitter Version 1918 (3-21-07)
Copyright 1999,2000 Atmel Corporation
Unknown cell : id00001
Reading input file failed ...

I have tried to narrow it down by creating a minimal case that provokes this but has been unsuccessful this far. All the minimal cases are fitted successfully. It is when I am close to the full design this happens. I have partioned the design in separate chunks that individually fit into a 1508 and I cannot find that the sum of the consumed resources would exceed the total amount of available resources.

Have you seen this type of errors? Did you find the root cause for these kind of errors?

[hoglet67]

Have you seen this type of errors? Did you find the root cause for these kind of errors?

Yes I have, and the cause is usually something unexpected in the EDIF file.

If possible, could you attach:

• your verilog source
• the .edif file
• a log of yosys running

[MattisLind]

First of all I need to tell that I am using VHDL, not verilog. I changed your script a bit so that it runs GHDL instead. It seems to work although I haven't tried the resulting JEDEC file yet. Then I like to say that I am not very fluent in VHDL either so it might very well be my stupid VHDL code that is causing all this.

After some trial and error I think I managed to nail it down to one single construct in VHDL. I managed to rewrite this into something that actually do pass the fitter. But I will surely run into similar issues in the future so if you can tell me what to look for in the EDIF and / or log that indicate the problem I would appreciate it.

Thanks a lot!

/Mattis

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity minimalcase is
port (
  data: inout std_logic_vector(7 downto 0);
  readPort0: in std_logic;
  readPort6: in std_logic
  );
end entity minimalcase;
architecture rtl of minimalcase is

begin

  data <= "11111111" when readPort0 = '1' else
          "00000000" when readPort6 = '1' else
          "ZZZZZZZZ";

end architecture rtl; 

This gives:

Atmel ATF1508 Fitter Version 1918 (3-21-07)
Copyright 1999,2000 Atmel Corporation
Unknown cell : id00001
Reading input file failed ...

yosys.log minimalcase.edif.txt

[hoglet67]

You just need to look in the EDIF file to see what id00001 is.

In this case it's:

    (cell (rename id00001 "$_TBUF_")
      (cellType GENERIC)
      (view VIEW_NETLIST
        (viewType NETLIST)
        (interface
          (port A (direction INPUT))
          (port E (direction INPUT))
          (port Y (direction OUTPUT))
        )
      )
    )

This should be mapped to a TRI cell by the -toutpad option in the iopadmap command in the yosys script:

iopadmap -bits -inpad INBUF Q:A -outpad BUF A:Q -toutpad TRI ENA:A:Q -tinoutpad bibuf EN:Q:A:PAD

For some reason in your case this isn't working.,

I wonder if it's because in the VHDL you have defined the data port as inout, but it's actually only being used as an output?

Does changing the data port from inout to out help?

[MattisLind]

I just tried to change it into "out" only and there is no difference. Still same error message.

minimalcase.edif.txt yosys.log

[hoglet67]

OK, leave this with me and I'll try to work out what's wrong. It may be a few days...

It would be interesting to see the same test case in Verilog has the same issue.