Pre assign pins to the fitter?

[MattisLind]

Do you have any idea if it is possible to pre-assign pins for the fitter?

It seems like the fitter somehow allow this; There is a -preassign option to the fitter which takes argument Try | Keep | Ignore. According to the docs/FITTER2.txt there is an option -strategy pinfile. I guess that you could add a "pinfile" here.

What could be the format of said pinfile?

This Microchip resource (https://microchip.my.site.com/s/article/Making-pin-assignment-for-ATF15xx-CPLD-in-VHDL) mentions that with Prochip designer it is possible to specify attributes in the VHDL code which ends up in the EDIF file. That is probably not supported by default with GHDL. Perhaps it could be using some magic?

I would like, if possible, to keep the SPI-port signals close so that it is easier to make the traces equal in length.

Do you know of any way to pre-assign pins, will it be EDIF file modifications or external pinfile (what kind of format would that have?)

Best regards,

/Mattis

[hoglet67]

Yes it is, but the fitter is very fussy about formatting.

Here's a minimal example:

CHIP "mmu" ASSIGNED TO AN PLCC84
CLKX4      : 83
DATA_0     : 37
DATA_1     : 39
DATA_2     : 40
DATA_3     : 41

It's very fussy about the presence of first line.

You then need to specify

-preassign keep

By default, the pin file is expected to have the same base name as the input EDIF file, and a .pin suffix.

My fitter script automatically generates a pin file from comments in the verilog: https://github.com/hoglet67/atf15xx_yosys/blob/master/examples/mmu/mmu.v#L173

If you want to manually generate this, and you are using my script, then you need to comment out this line: See: https://github.com/hoglet67/atf15xx_yosys/blob/master/run_fitter.sh#L93

[MattisLind]

Thanks a lot. Exactly what I needed!

[MattisLind]

Hello David!

What is your experience when using the -preassign keep and a pin-file? Does it keep the same pins allocated for the same signals even though you change the equations a tiny bit or add one new IO?

I had 56 IO used out of 64 on the 84 pin ATF1508 and needed to add three new outputs. These outputs simply buffered corresponding inputs so not much logic involved. After this tiny change half the pins moved around. Half stayed as they were before. I do have -preassign keep. I was thinking it would fail if it was unable to fit it but otherwise create a non-optimal fit instead of creating a completely new pin-layout.

Sort of the idea of programmable logic that you could alter it slightly in-circuit to make it fit changed requirements, right?

Many years ago I had a WinCUPL design where the pins were fixed. I just had to fit the equations and of course that worked just fine. Of course WinCUPL is lower level so perhaps it doesn't use a fitter at all.

Your input regarding this matter is highly appreciated!

[hoglet67]

What is your experience when using the -preassign keep and a pin-file? Does it keep the same pins allocated for the same signals even though you change the equations a tiny bit or add one new IO?

I do have -preassign keep. I was thinking it would fail if it was unable to fit it but otherwise create a non-optimal fit instead of creating a completely new pin-layout.

It has worked for me, but you need to pay attention to the log/report file. If it struggles to fit the design with the assigned pins, then it will ignore them. But the log/report file does tell you it's done this.

Many years ago I had a WinCUPL design where the pins were fixed. I just had to fit the equations and of course that worked just fine. Of course WinCUPL is lower level so perhaps it doesn't use a fitter at all.

WinCUPL does actually use the same fitter underneath.

Can you post your log/report file here?

Dave