CMAC 0 and 1

[luyong6]

Hi, I noticed that in the submodule/cmac directory, it created two CMAC IPs, for example,

alveou200_board     = cmac_ALVEOu200_0 cmac_ALVEOu200_1

However, it seems only one has been instantiated in the design. Why, and what is the second CMAC module used for?

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Besides, Vivado 2020.1 complains an error about the interface type in Alveo U280's block_design.tcl:

1740   set m_axis_session_lup_req [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_tlm:1.0 m_axis_session_lup_req ]

lup_req uses axis_tlm, and the upd_req uses axis_rtl. I suppose they should use the same interface type.

1750    set m_axis_session_upd_req [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_session_upd_req ]

[mariodruiz]

Hi,

Some cards have two physical 100 Gbps interfaces. Therefore, each of these IP is tailored to the specific physical interface. GT selection and so on.

I have not tried the design in Vivado 2020.1. That block design was generated with Vivado 2018.3. What if you remove/comment these two lines and do the connection manually after the block design is created?

Please, if you go ahead with a U280 design, before downloading the bitstream double check that pin D32 is set to 0, https://www.xilinx.com/support/answers/72926.html otherwise the board is likely to brick. I think I fixed that, but, I have never tried that design in an U280.

[luyong6]

Thanks Mario. For those cards who have two 100G cages, Limago doesn't require two CMACs working together, it only uses one, which can be either CMAC_0 or CMAC_1. Right?

[mariodruiz]

The current project, only requires one interface. But, there's nothing preventing to use both interfaces at the same time. Two Limago instances will be a good example.

Were you able to create the project in Vivado 2020.1?

[luyong6]

I am using a board with VU37P similar to U280. Vivado 2020.1 also reported two combintation loops in the DRC check.

#Suppress the combination loop
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets bd_wrapper_i/bd_i/interface_0_handler/TCP/iperf2_client_1/inst/client_U0/regslice_both_closeConnection_V_V_U/ibuf_inst/s_OpenConnResponse_V_TVALID_0]
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets bd_wrapper_i/bd_i/interface_0_handler/TCP/iperf2_client_1/inst/server_U0/regslice_both_listenPort_V_V_U/ibuf_inst/s_App2RxEngResponseID_V_V_TREADY]

After suppressing them, I was just able to build a bitstream out. Are these two combinational loops similar to what you had found in Vivado 2018? (Mentioned in the README.md on the front page). Do they really matter and shall we look deep into them?

(Another tip is, when you choose the DDR channel, please pick up a bank near the other part of logic. For me, XDMA, CMAC, and DDR4MC are all in SLR0 now and the timing was closed without any problems. (At beginning I put the DDR4MC at SLR2 and that was a tragedy. )

Would you please give me some suggestions for the hardware test? I have two same VU37P cards.

1. Can I use just one server and one card (one ethernet port), is there any "loop-back" wire? Doesn't Limago support such test?
2. If I use one server and install two cards, and connect their ethernet ports together, and program both cards with Limago, does it work?
3. Do I need other NICs? Swithes?

Thank you very much.

[mariodruiz]

Yes, these are the combinational loop I saw. I am not sure, if it safe to ignore them. Other option, is to include a AXI4-Slice register.

I need to have another look at the memory bank, the Alveo U280 does not have a memory bank in SLR2. It would be ideal to have the memory bank in the same SRL as the TCP part to avoid crossing SLRs.

To answer your questions.

1) You could do a loopback in the same interface, there's a special loopback QSFP28 module. You could also configure the CMAC to be in a loopback mode. It think that can be done a run time. In theory it should be supported, but I never tested it. 2) Yes, it should. You can run the iperf hardware implementation from software. If you expand this section, you can see how to run hw iperf2. However, you may want to change the IP and MAC address of one of the boards. It also can be done at run time. 3) You don´t. But, for debugging it is much easier if you have a NIC

Hopefully this helps. Let me know if I can help with something else.

[luyong6]

Thanks Mario, I am buying the cables now.