Currently, act_bit and weight_bit parameters may only be powers of two (1,2,4,8,16,32). Apart from the fact that other values will not evenly divide 64, there is no reason you could not support other values. Indeed, those interested in modeling possible ASIC/FPGA architectures aren't going to want to be limited to powers of two.
Obviously, this would require a little bit of work to figure out the bit-packing scheme and mask out unused bits.
Currently,
act_bitandweight_bitparameters may only be powers of two (1,2,4,8,16,32). Apart from the fact that other values will not evenly divide 64, there is no reason you could not support other values. Indeed, those interested in modeling possible ASIC/FPGA architectures aren't going to want to be limited to powers of two.Obviously, this would require a little bit of work to figure out the bit-packing scheme and mask out unused bits.