Additional context
The architectural (where present) PMU version is a useful implementation detail. It's not part of the cpuid, nor it depends on armv8-revision; instead it's fully described by a debug feature register -- ID_AA64DFR0_EL1[11:8] PMUVer; additionally ID_AA64DFR0_EL1[35:32] PMSVer is becoming increasingly useful. Reporting the numerical value of those DFR fields would be valuable.
Furthermore, it's worth considering reporting the architectural PMU events per the given implementation [1], but that's more involved as it requires a major SoC record overhaul.
Describe the system System name: any SoC with ID_AA64DFR0_EL1[11:8] PMUVer != 0 Vendor name: multiple SoC name: multiple URL to product page: https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/ID-AA64DFR0-EL1--AArch64-Debug-Feature-Register-0?lang=en
Additional context The architectural (where present) PMU version is a useful implementation detail. It's not part of the cpuid, nor it depends on armv8-revision; instead it's fully described by a debug feature register -- ID_AA64DFR0_EL1[11:8] PMUVer; additionally ID_AA64DFR0_EL1[35:32] PMSVer is becoming increasingly useful. Reporting the numerical value of those DFR fields would be valuable.
Furthermore, it's worth considering reporting the architectural PMU events per the given implementation [1], but that's more involved as it requires a major SoC record overhaul.
[1]