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ht32-rs / ht32f5xxxx-hal

A Rust HAL for the ht32f5xxxx family of chips
BSD Zero Clause License
9 stars 3 forks source link

Bump cortex-m from 0.6.2 to 0.6.3 #10

Closed dependabot[bot] closed 4 years ago

dependabot[bot] commented 4 years ago

Bumps cortex-m from 0.6.2 to 0.6.3.

Release notes

Sourced from cortex-m's releases.

v0.6.3

Added

  • Initial Cortex-M Security Extension support for armv8m
  • UDF intrinsic
  • Methods to enable/disable exceptions in SCB

Fixed

  • Fix bug in asm::delay not updating status clobber flags
  • Swapped to llvm_asm! to support inline assembly on new nightlies
  • Our precompiled assembly routines have additional debug information
  • ITM is_fifo_ready improved to support armv8
  • Cache enabling moved to pre-built assembly routines to prevent possible undefined behaviour
Changelog

Sourced from cortex-m's changelog.

[v0.6.3] - 2020-07-20

Added

  • Initial Cortex-M Security Extension support for armv8m
  • UDF intrinsic
  • Methods to enable/disable exceptions in SCB

Fixed

  • Fix bug in asm::delay not updating status clobber flags
  • Swapped to llvm_asm! to support inline assembly on new nightlies
  • Our precompiled assembly routines have additional debug information
  • ITM is_fifo_ready improved to support armv8
  • Cache enabling moved to pre-built assembly routines to prevent possible undefined behaviour
Commits
  • 39ee966 Merge #250
  • 2e44cd8 Bump version to 0.6.3
  • 358be5d Merge #249
  • 6717d4b Update CHANGELOG with 0.6.3 backports
  • 202cb2d Always link pre-built asm, required for new cache management functions
  • b7ff5f7 Allow the taken flag to be optimized out
  • cb6a61a Add a function to get SHCSR enable bit positions
  • b607b35 Use assembly sequences to enable caches.
  • 33f0318 Correct the documentation for the SCB::set_pendst function
  • f58e5e1 ITM: don't test reserved bits in is_fifo_ready
  • Additional commits viewable in compare view


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