Network on a Chip (NoC) implementation

[hughperkins]

Need a network on a chip implementation

Firstly, what is network on a chip? See https://amstel.estec.esa.int/tecedm/NoC_workshop/GinosarNOC_Tutorial.pdf Buses are becoming spaghetti, so chips nowadays use an internal packet-switching network instead.

(slide from presentation linked above)

Then the tasks for NoC for VeriGPU are:

• what implementations currently exist?
  • how is RaveNoC? https://github.com/aignacio/ravenoc
• what do similar projects use?
  • e.g. what does Vortex use? https://github.com/vortexgpgpu/vortex (it's possible they use the FPGA-native routing/networking structures, since they target specifically FPGAs)
• for any existing NoC implementations:
  • good points?
  • anything missing, or not quite working yet?
  • how recently maintained are they? (i.e. are there recent commits?)
  • have they already been used in actual taped-out ASICs?
  • if it looks good, could we get a full independent verification? (you would create this, in a new repo, your own project :) )
  • ideally, including formal verification (again, your own repo, your own project :) )
• of course, you could provide your own implementation too, but NoC is complex, so simply verifying someone else's NoC is hard. Bear in mind that 80% of semiconductor development in industry is spent on verification.
• what configuration(s) do you recommend for a GPU? (Please let me know if you need more information on what logical architecture I'm envisaging).
• Clear documentation on how to integrate the NoC with VeriGPU
• Ideally, PR that integrates the NoC with VeriGPU (could be multiple PRs)

[kevinpinto98]

Hi @hughperkins I am interested in implementing the NoC for VeriGPU. Kindly let me know if this is still available. Also could you let me know in brief the steps to be followed in order to contribute to this repository.