Open daveythacher opened 4 years ago
The comment is there, describing that we want to minimize each of the entries as we have to accomodate empty slots
The code is based on observing the actual behavior of the limited documentation available and measuring. If you see improvements and can measure the results, send a pull request.
Currently you have OE logic limited to range 50-3000ns. Why? This is not likely required, the current logic supports 16 to 16384. You could improve this to support just about anything in 8ns steps.
It looks like you use the 500MHz clock to drive the PWM, but scale it down to 125MHz. (I am guessing this is need?) The OE value is divided by four which produces the divider for the PWM logic. You then set the PWM value and period as two raised to the BCM bit multiplied by two. So you send a 100 percent duty cycle non repeating pulse to OE. You use inverted logic to handle active low.
You could use 500MHz clock divided by four. Then you could use period and value set to the OE value divided by eight. The alternative is the divider based on lsb-ns value. You could do simple division tests to find a scaler.
While your at it you could optimize a few things. https://github.com/hzeller/rpi-rgb-led-matrix/blob/c8f5a83be52d400ab21c223e829a11754a3dd2a7/lib/gpio.cc#L625
This really needs a comment: (Divide by 8? Why so many?) https://github.com/hzeller/rpi-rgb-led-matrix/blob/c8f5a83be52d400ab21c223e829a11754a3dd2a7/lib/gpio.cc#L641-L648