Open 290787665 opened 7 months ago
Sorry, I no longer work on FPGA-related projects and currently don't have any hardware to reproduce this. Experiences from my lab mate suggest that this might be related to BRAM settings in Vivado and dtype in Python side. You can try to play around with that. PR is also welcomed if you come up with any fixes.
when I tried to transfer 16bit and 32bit data, data will be lost. Code and results as follow:
![QQ截图20231206192543](https://github.com/iamNCJ/PYNQ-CDMA-Driver/assets/70091514/4e107a44-0cbd-4600-961b-5b7e1a77c664)
My block design is as follow:![QQ截图20231206192736](https://github.com/iamNCJ/PYNQ-CDMA-Driver/assets/70091514/01397eb3-1988-4fe8-81e3-add16240bed5)
I tried your example, and the result is still incorrect. Maybe there is an issue with my block design?![QQ截图20231206200551](https://github.com/iamNCJ/PYNQ-CDMA-Driver/assets/70091514/a8e11e36-d8b0-4057-a4ad-2123dc309f23)
我这里就敲中文吧,我发现在读写连续数据的时候,每隔32bit就会丢失32bit的数据
但是当我对bram一个一个写入,再一个一个读取的时候,就不会出现这种丢失数据的情况,但是对DDR一个一个写入一个一个读取依然会有这个情况。我是新手,不太了解硬件这一块,如果您有空能帮我看看是最好的,谢谢!
Thanks for replying!