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ibirnbaum / zephyr4zedboard-tutorial

Tutorial on how to boot Zephyr on the Avnet/Digilent Zedboard, includes building a FPGA bitstream and the First Stage Boot Loader (FSBL)
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axi_gpio_switches_leds.overlay file #1

Open jbalasch opened 5 months ago

jbalasch commented 5 months ago

Thanks for the nice tutorial!! Would it be possible to add the axi_gpio_switches_leds.overlay that enables the AXI GPIO controller IP core(s) in the design?

ibirnbaum commented 4 months ago

@jbalasch Thank you, I'm glad if you find it useful! I'll add the overlay file to the zedboard branch of my zephyr fork as soon as possible, I wonder where those went...

Please note that the zedboard branch hasn't been synced against the main branch for quite some time now, so it might need some tinkering to use the Zedboard definition with the current main. The upcoming hardware description model v2 and my proposed clock control driver for the Zynq will likely lead to a need to update the device tree before the Zedboard definition can be PR'ed.

In case you're currently developing for the Zynq with the intent to use the GEM Ethernet controller: there seems to be a problem with the packet data DMA when using bitstreams built with the most recent Vivado version. There is a fix for that which isn't too complicated, I ought to PR a fix for that...

ibirnbaum commented 4 months ago

@jbalasch Also, another thing I noticed regarding Vivado is that there is a faulty template for the Zedboard in some Vivado versions. When configuring the Processor System in Vivado, double-check the clock configuration in the 'Basic Clocking' tab: the value of the field 'Input Frequency(MHz)' must be 33.333333. If you have a faulty Zedboard template in your Vivado installation, the value will be 50 instead, and not a single clock will work correctly once the FSBL has completed, as the Zedboard definitely only exists with a 33.3 MHz crystal.