Power Hardware Abstraction layer base

[ojayanth]

  - No Raw SCOM from BMC side product code, uses SBE chip-ops only.   - Debug applications/tooling go through Cronus or ePdbg path                - Direction :Use cronus for Scanrings and chip specific operations and Dump use SBE ops and do software debug.   - Cronus support, need a mechanism to debug failure- ePdbg is one of the proposed option discussed.   - BMC version of targeting.

• Special wake-up is handled by SBE , no bcc related changes required.

[ojayanth]

Provide infrastructure code to support for chip specific Hardware access, HWPF( Hardware procedure access) and SBE interactions.

Use-cases:

• [ ] BMC should provide support to execute Step-0 and FFDC HWPs.
• [ ] BMC native SCOM support required for SBE debug ( Proc and Pervasive target)
• [ ] CFAM support.
• [ ] Lab/Customer Debug ( OPAL)
• [ ] get/put SCOM, FPR, memory(proc pba) using SBE.
• [ ] SCAN support ( Use Cronus) for chip team debug
• [ ] Jpiranha( processor Debug tool) support for Phyp Debug
• [ ] Host Processor start/stop/step/sreset/breakpoint.( using SBE).

[ojayanth]

No open issues , closing this epic