pdbg: openbmc required HW access API's definition

[ojayanth]

Finalize the design direction to use common HW access API's to check HW states and othe miscellaneous functions.

Requirements details available here #2919 #3119 #3120

[ojayanth]

Discussed with @amitay and the direction is to create new library in pdbg repositories to add all required hardware specific wrapper function required for opebmc.

[ojayanth]

Int checkattn( bool & state ) global attention status register and mask for SBE error. If both these bits are ‘1’ for any proc the attention gpio should have gone active and triggered the attention handler. global interrupt status register is cfam 0x1007, global interrupt mask is cfam 0x100d, sbe error is bit 30

Int setSBEState(const Target* procTarget, SBE_STATE sbeSatate) { Update CFAM 2986 with input value. }

Int getSBEState((const Target* procTarget, SBE_STATE& sbeSatate) { Read cfam 2986 In case the SBE state is marked as CHECK_CFAM then SBE's //PERV_SB_MSG_FSI register must be checked to see if SBE is booted or   //NOT. static const uint32_t FSXCOMP_FSXLOG_SB_MSG_FSI = 0x00002809ull; }

//check SBE IPL completed. Int isPrimarySBEIplDone( bool &o_sbeIplDone) { Read SBE message register ( l_sbeReg.) if( (SBE_STATE_RUNTIME == l_sbeReg.currState) ||   (SBE_STATE_RUNTIME == l_sbeReg.prevState)) { o_sbeIplDone = true; break; } }

Additional Info:

Mailbox scratch 15 (CFAM 2986, SCOM 0x50186) – BMC SBE state register

• BMC will use this register to keep track of the SBE state (being hreset or running)

enum SBE_STATE  {   SBE_STATE_NOT_USABLE = 0x00000000,   SBE_STATE_BOOTED = 0x00000001, SBE_STATE_CHECK_CFAM = 0x00000002,   SBE_STATE_DEBUG_MODE = 0x00000003, SBE_STATE_FAILED = 0x00000004,   SBE_STATE_UNKNOWN = 0x00000005,   SBE_STATE_INVALID = 0xFFFFFFFF,  }; . /// @brief A structure (bitfield) representing the SBE messaging register typedef union sbeMsgReg { struct {

ifdef _BIG_ENDIAN

    uint32_t sbeBooted : 1; ///< SBE control loop initialized
    uint32_t asyncFFDC : 1; // < async ffdc present on sbe
    uint32_t reserved1 : 2; ///< Reserved
    uint32_t prevState : 4; ///< Previous SBE state
    uint32_t currState : 4; ///< Current SBE state
    uint32_t majorStep : 8; ///< Last major istep executed by the SBE
    uint32_t minorStep : 6; ///< Last minor istep executed by the SBE
    uint32_t reserved2 : 6; ///< Reserved

else

    uint32_t reserved2 : 6; ///< Reserved
    uint32_t minorStep : 6; ///< Last minor istep executed by the SBE
    uint32_t majorStep : 8; ///< Last major istep executed by the SBE
    uint32_t currState : 4; ///< Current SBE state
    uint32_t prevState : 4; ///< Previous SBE state
    uint32_t reserved1 : 2; ///< Reserved
    uint32_t asyncFFDC : 1; // < async ffdc present on sbe
    uint32_t sbeBooted : 1; ///< SBE control loop initialized

endif

};
uint32_t reg; ///< The complete SBE messaging register as a uint32

} sbeMsgReg_t;

/**

• @brief Enumeration of SBE states */ typedef enum sbeState { SBE_STATE_UNKNOWN = 0x0, // Unkown, initial state SBE_STATE_IPLING = 0x1, // IPL'ing - autonomous mode (transient) SBE_STATE_ISTEP = 0x2, // ISTEP - Running IPL by steps (transient) SBE_STATE_MPIPL = 0x3, // MPIPL SBE_STATE_RUNTIME = 0x4, // SBE Runtime SBE_STATE_DMT = 0x5, // Dead Man Timer State (transient) SBE_STATE_DUMP = 0x6, // Dumping SBE_STATE_FAILURE = 0x7, // Internal SBE failure SBE_STATE_QUIESCE = 0x8, // Final state - needs SBE reset to get out

  // Max States, Always keep it at the last of the enum and sequential SBE_MAX_STATE = 0x9, // Don't count this in the state, just to intialize the state variables SBE_INVALID_STATE = 0xF, } sbeState_t;

  //In the MPIPL path master SBE's state should not change, put the slave SBE state to SBE_STATE_CHECK_CFAM