Open jimga150 opened 4 years ago
Hello, I am getting the same error. Did you figure out what the problem was?
Hello, sorry for the delay. For both of you - which VHDL system are you using (ISE/Vivado/something else) and are you using the code exactly as here? I will try to replicate the problem.
Hello, sorry for the delay. For both of you - which VHDL system are you using (ISE/Vivado/something else) and are you using the code exactly as here? I will try to replicate the problem.
Hello! I was trying it on Xilinx ISE Design Suite.
Same here. I'm using 14.7, with the code unchanged.
When running the testbench given, i get this output:
I'm trying to understand the test bench, and i'll continue to do so, but i thought i might ask here in case the dev has an answer for me. Thanks!